Memory Control Unit Non-Consecutive LBA Write Strategy
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Solution Overview
Problem
The existing memory systems face performance deterioration and increased write time when writing data with non-consecutive logical block addresses (LBAs) due to the need for frequent reassignment of blocks and data transfer in NAND-type flash memory systems.
Innovation Solution
A memory system and method that allow data to be written in the same first block even if the second block's address is not consecutive to the already written data, utilizing a control unit to manage and write data in a way that reduces the need for new block assignments and data transfers by using existing blocks for additional writes and storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the controller assigns a new large block and transfers already written data when LBAs are inconsecutive, then the data can be written in the NAND-type flash memory, but the write time increases and write performance deteriorates
Solution Approach 1:
The patent applies preliminary action by pre-managing the mapping between LBAs and physical block addresses in a translation layer before actual data writing occurs. The controller maintains a mapping table that tracks which LBAs are allocated to which physical blocks, allowing it to proactively determine that inconsecutive LBAs can share the same physical block, thus avoiding the need for new block assignments and data transfers when such conditions arise.
Solution Approach 2:
The patent introduces an intermediary translation layer between the logical block addresses (LBAs) and physical block addresses in the NAND flash memory. This intermediary mapping mechanism decouples the logical address space from the physical storage structure, enabling flexible allocation where multiple LBAs can map to the same physical block regardless of consecutiveness, thereby eliminating the performance penalty associated with traditional sequential block assignment.
2Reliability
If the controller assigns a new large block for inconsecutive LBAs, then data can be stored, but the number of block assignments and data transfers increases
Solution Approach 1:
The patent applies universality by designing a physical block structure that can serve multiple logical purposes simultaneously. A single physical block can accommodate multiple LBAs that are not consecutive, allowing the same storage space to be reused for different logical addresses. This multi-functional use of physical blocks reduces the frequency of new block allocations and minimizes data transfer operations, directly reducing write time while maintaining reliable data storage.
3Productivity
If data is written in units of LBA with consecutive addresses, then data can be successively written in the assigned large block, but this scheme cannot be applied when LBAs are inconsecutive
Solution Approach 1:
The patent applies dynamics by implementing a flexible mapping strategy that adapts to different LBA patterns. The translation layer dynamically determines whether LBAs are consecutive or inconsecutive and adjusts the physical block allocation accordingly. When LBAs are inconsecutive, the system dynamically updates the mapping to allow multiple LBAs to share the same physical block, enabling successive writing operations to proceed efficiently without requiring sequential physical block assignment, thus maintaining high write speed while handling diverse address patterns.
Data Source
AI summary
A memory unit includes a plurality of first blocks each having a first block size. Each of the first blocks stores data of a plurality of second blocks each having a second block size which is smaller than the first block size. A control unit writes the data of the second block in the first block. The control unit is configured such that in a case where the second block to be written is a block that is to be written in the same first block as the second block that is already written in the first block, the second block to be written is written in the same first block even if an address of the second block to be written is not consecutive to an address of the second block that is already written in the first block.