Memory Device Control Logic Merging for Multi-Plane Area Reduction
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Solution Overview
Problem
Existing memory devices require a significant physical area for control logics to independently manage operations across multiple planes, leading to inefficiencies in space utilization.
Innovation Solution
A memory device architecture that includes N planes, a signal generation block for decoding control codes, N operation performing blocks for executing operations on each plane, a signal transmission block for transmitting operation control signals, and a selection control block for generating selection signals based on input commands, addresses, and clocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple control logics are included to independently control operations of multiple planes, then the independence and reliability of plane operations is improved, but the physical area occupied by control logics increases
Solution Approach 1:
The patent merges multiple control logics into a single shared control logic that can independently control multiple planes. The control logic includes a command decoding unit that decodes commands to determine target planes, and a control signal generation unit that generates control signals for selected planes. This consolidation maintains operational independence through software/control logic management while significantly reducing the physical area occupied by control circuits.
Solution Approach 2:
The control logic is designed with multi-functionality to handle operations across multiple planes. The command decoding unit universally processes commands for any plane, and the control signal generation unit can generate appropriate control signals for any selected plane. This universal design allows one control logic to replace multiple dedicated control logics, reducing area while maintaining the ability to independently control each plane's operations.
2Reliability
If separate control logics are used for each plane, then the control precision and reliability for each plane is improved, but the device complexity increases
Solution Approach 1:
The patent combines multiple separate control logics into one integrated control logic unit. This control logic includes a command decoding unit that universally decodes commands for any plane, and a control signal generation unit that selectively generates control signals for the target plane. This merging reduces device complexity by eliminating redundant control logic instances while maintaining precise control over each plane through selective signal generation based on decoded command information.
3Productivity
If multiple control logics are implemented to enable independent plane operations, then the productivity of memory operations is improved, but the physical area occupied by control circuits increases
Solution Approach 1:
The patent merges multiple control logics into a single control logic that can sequentially and independently control multiple planes. The command decoding unit decodes incoming commands to identify target planes, and the control signal generation unit generates plane-specific control signals. This allows the memory device to perform operations on different planes in sequence (e.g., erase operation on first plane while read operation occurs on second plane), maintaining high productivity while minimizing control circuit area through consolidation.
Solution Approach 2:
The control logic dynamically adapts its behavior based on the decoded command and target plane identification. The control signal generation unit dynamically selects which plane to control and generates appropriate control signals based on real-time operation requirements. This dynamic operation allows a single control logic to efficiently manage multiple planes with different operation states, maintaining high productivity without requiring static dedicated control logic for each plane.
Data Source
AI summary
A memory device comprises: N planes each including a plurality of memory cells, a signal generation block suitable for: selecting a control code corresponding to a selection signal from N control codes respectively corresponding to the N planes, and generating an operation control signal by decoding the selected control code, N operation performing blocks each suitable for performing a predefined operation on a corresponding plane of the N planes according to a value of the operation control signal, a signal transmission block suitable for transmitting the operation control signal to one of the N operation performing blocks through a path corresponding to the selection signal among N paths that connect the signal generation block to the respective N operation performing blocks, and a selection control block suitable for generating the selection signal in response to an input command, an input address and an input clock.