3D Memory Control Logic Vertical Routing
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Solution Overview
Problem
Three-dimensional (3D) memory device architectures face complex and congested routing designs due to the need to electrically connect DRAM cells to control logic circuitry, such as sub-word line drivers and sense amplifiers, which can impede performance and efficiency.
Innovation Solution
The microelectronic device design includes a closed memory architecture where CMOS circuitry sense amplifiers are vertically positioned over the memory cells, allowing for more space above the array regions and facilitating rearrangement of control logic devices, thereby improving routing efficiency and reducing timing delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If control logic devices are placed in a base control logic structure underlying the memory array, then electrical connection to DRAM cells is achieved, but routing becomes complex and congested
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement where control logic devices are positioned beneath the memory array to a three-dimensional architecture where control logic devices are vertically stacked above the memory array. This dimensional change allows routing structures to extend vertically through the stack, significantly reducing horizontal routing congestion and improving signal paths between memory cells and control logic.
2Ease of operation
If control logic devices are positioned to electrically connect to DRAM cells through vertical routing structures, then connectivity is achieved, but routing design becomes congested
Solution Approach 1:
The invention utilizes the vertical dimension by stacking control logic devices above the memory array, allowing routing structures to traverse vertically through multiple layers. This eliminates the need for complex horizontal routing around peripheral regions and simplifies the overall routing design while improving efficiency.
Solution Approach 2:
The patent implements a nested architecture where control logic devices are positioned within the vertical stack above the memory array, with routing structures passing through intermediate layers. This nesting approach allows multiple functional elements to be integrated in a compact vertical arrangement, reducing routing complexity compared to planar expansion.
Data Source
AI summary
A microelectronic device is disclosed that incudes array regions individually comprising memory cells comprising access devices and storage node devices; digit lines coupled to the access devices that extend in a first direction; and word lines coupled to the access devices that extend in a second direction orthogonal to the first direction. Digit line exit regions horizontally alternate with the array regions in the first direction; sense amplifier sections comprising sense amplifier circuitry vertically overlie and horizontally overlapping the digit line exit regions; and routing structures within horizontal areas of the digit line exit regions, couple the sense amplifier circuitry of the sense amplifier sections to the digit lines.