Memory Control Logic for Reduced-Data-Rate Testing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-throughput memory architectures, such as XDR2 and TBI, face issues with invalid command/address (CA) commands during reduced-data-rate (RDR) testing due to their high-speed fully differential CA channels, which are not compatible with existing RDR testing methods.
Innovation Solution
Implementing a memory system with control logic that allows for sub-field sampling of CA packets during RDR operating mode, reducing the effective data rate by decoding every other or every fourth address bit, and storing the remainder of the address bits in a register to maintain CA packet validity and enable testing with low-speed equipment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If RDR testing is performed on high-speed fully differential CA channels, then low-speed test equipment can be used, but invalid CA commands occur due to incompatibility
Solution Approach 1:
The CA channel is segmented into two independent parts: a high-speed fully differential CA channel for normal operation and a low-speed test CA channel for RDR testing. This segmentation allows each channel to operate at its optimal speed without interference, resolving the contradiction between using low-speed equipment and maintaining command validity.
Solution Approach 2:
A control logic unit acts as an intermediary between the test equipment and the memory device. This intermediary translates commands from the low-speed test CA channel into valid commands for the high-speed CA channel during normal operation, ensuring compatibility while maintaining reliability.
2Productivity
If CA channel runs at same speed as DQ channel, then high throughput is achieved, but RDR testing becomes unavailable
Solution Approach 1:
The CA channel operates dynamically at different speeds depending on the mode: high-speed fully differential mode during normal operation for maximum throughput, and low-speed mode during RDR testing for compatibility with test equipment. This dynamic operation resolves the contradiction between throughput and testing capability.
Solution Approach 2:
The CA channel is designed with multi-functionality to serve both high-speed data transmission during normal operation and low-speed testing during RDR mode. This universal design allows the same channel to support both high productivity and adaptability to different testing requirements.
Data Source
AI summary
Embodiments of a memory device are described. This memory device includes a signal connector which is electrically coupled to a command/address (CA) link, and an interface circuit, which is electrically coupled to the signal connector, and which receives CA packets via the CA link. A given CA packet includes an address field having address information corresponding to one or more storage locations in the memory device. Moreover, the memory device includes control logic having two operating modes, where, during a first operating mode, the control logic decodes address information in the CA packets using full-field sampling, and, during the second operating mode, the control logic decodes a portion of the address information in the CA packets using sub-field sampling.