Memory Control Circuit Phase Detection Timing Adjustment
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Solution Overview
Problem
In DDR RAMs, the data strobe signal may not comply with specifications due to uncorrected signal delays, leading to incorrect writing of data into memory cells when the time interval TDQSS does not meet the required range, causing data integrity issues.
Innovation Solution
A phase detection method and memory control circuit that detects the phase difference between the data strobe signal and the clock signal, generating phase lead/lag detection results to adjust the delay of the odd/even data separation signal, ensuring correct timing for data writing by delaying or bypassing the data accordingly based on the phase detection results.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the frequency of the clock signal is increased to improve data accessing speed, then the data accessing speed is improved, but the signal delay in the circuit system increases causing the data strobe signal to not comply with specifications
Solution Approach 1:
The patent applies preliminary action by detecting the phase difference between the data strobe signal and clock signal before data writing operations. The phase detection module measures the phase relationship in advance, and the delay control module pre-adjusts the timing of odd/even data to compensate for potential timing violations, ensuring that data is written at the correct time even when clock frequency is increased.
Solution Approach 2:
The patent implements feedback by using the phase detection module to continuously monitor the phase difference between the data strobe signal and clock signal. The delay control module receives this phase information as feedback and dynamically adjusts the delay of odd/even data accordingly, creating a closed-loop control system that maintains timing specification compliance despite variations in clock frequency.
2Ease of operation
If the data strobe signal timing is not properly adjusted, then the data accessing operation is simplified, but the data cannot be guaranteed to be written into memory cells correctly
Solution Approach 1:
The patent introduces an intermediary mechanism by separating the data stream into odd and even data paths. The delay control module selectively applies delay only to the odd data path when phase difference exceeds the threshold, while the even data path remains undelayed. This intermediary approach maintains simplicity for normal operations while ensuring correctness when timing issues are detected.
Solution Approach 2:
The patent applies parameter changes by dynamically adjusting the delay parameter of the odd/even data based on the detected phase difference. When the phase difference is within the threshold range, no delay is applied (simple operation). When the phase difference exceeds the threshold, the delay parameter is increased to compensate for timing violations, ensuring correct data writing while maintaining ease of operation for normal cases.
Data Source
AI summary
A memory control method includes: latching a clock signal to selectively generate a phase lead detection result and a phase lag detection result in response to a data strobe signal; delaying the data strobe signal to generate a plurality of delayed data strobe signals; latching the clock signal to generate a plurality of phase detection results in response to the delayed data strobe signals so as to correspond to the delayed data strobe signals; latching write data carried by a data signal according to rising/falling edges of the data strobe signal; performing odd/even data separation on the write data to generate a data separation signal carrying odd/even data corresponding to the write data; and in a situation where the data strobe signal leads the clock signal, delaying or bypassing the odd/even data carried by the data separation signal according to the phase detection results. A memory control circuit is provided.