Memory Control Circuit Pre-Read Optimization

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Solution Overview

Problem

Existing memory storage devices face reduced data reading efficiency when dealing with deep command sequences or large amounts of data, as pre-reading operations can instead hinder performance.

Innovation Solution

A memory control method that determines the necessity of a pre-read operation based on the total data amount and depth information of read commands, optimizing data reading by pre-reading data from logical units mapped to physical units in a rewritable non-volatile memory module.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If pre-read operation is performed for deep command sequences or large data amounts, then data reading efficiency should be improved, but actual reading efficiency decreases due to unnecessary pre-reading operations

Engineering Contradiction:
Improvedata reading efficiencyVSAvoidtime wasted on unnecessary pre-reading
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent changes the decision parameter for pre-read operations from a fixed rule to a dynamic evaluation based on command sequence depth and data amount thresholds. The controller evaluates whether the command sequence depth exceeds a first threshold and whether the data amount exceeds a second threshold before initiating pre-read operations, allowing adaptive adjustment of pre-read behavior based on actual workload characteristics

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent introduces a feedback mechanism where the controller continuously monitors command sequence depth and data amount metrics, and uses this information to dynamically control the execution of pre-read operations. This feedback loop prevents unnecessary pre-reading by evaluating current system state against predefined thresholds, thereby avoiding time waste while maintaining productivity benefits when pre-reading is actually beneficial

Inventive Principle:
Principle #23Feedback

2Speed

If pre-read operation is always performed, then next to-be-accessed data can be prepared in advance, but system complexity increases and performance deteriorates for certain command patterns

Engineering Contradiction:
Improvedata access speedVSAvoidcontrol logic complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent introduces two key parameters - command sequence depth threshold and data amount threshold - that dynamically control pre-read operation execution. This parameter-based control simplifies the decision logic compared to always performing pre-read, while still enabling fast data access when conditions warrant it. The thresholds act as simple gatekeepers that avoid complex predictive algorithms

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent makes the pre-read operation dynamic by conditioning its execution on real-time evaluation of command sequence characteristics. Rather than a static always-on pre-read mechanism, the system adapts pre-read behavior based on whether current workload patterns match scenarios where pre-reading provides benefit, thereby maintaining speed while reducing unnecessary operational complexity

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS11301311B2Memory control method, memory storage device, and memory control circuit unit
Publication Date: 2022.04.12 PHISON ELECTRONICS
  • US11301311B2 patent drawing
  • US11301311B2 patent drawing
  • US11301311B2 patent drawing

AI summary

A memory control method for a rewritable non-volatile memory module is provided according to embodiments of the disclosure. The method includes: receiving at least one first read command from a host system; and determining, according to a total data amount of to-be-read data indicated by the at least one first read command, whether to start a pre-read operation. The pre-read operation is configured to pre-read data stored in at least one first logical unit, and the first logical unit is mapped to at least one physical unit.