Memory Control Protection Using Toggled WE and Address Parity
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Solution Overview
Problem
Current memory systems lack effective methods to protect logic paths feeding address and control inputs to memories, with existing parity-based solutions only detecting 50% of single faults on address lines and failing to detect stuck-inactive or stuck-active faults in Write Enable (WE) signals.
Innovation Solution
A memory system that splits data into N separate memories, generates redundant parity and toggled bits for control signals and addresses, and uses error detection circuits to compare these across memories to detect faults, ensuring independent protection for control signals and addresses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If combined parity bit P(d+a) is used to protect data and address, then data protection is improved, but address fault detection capability deteriorates (only 50% of single faults detected)
Solution Approach 1:
The patent divides the protection mechanism into separate components: data parity bits for data protection and address parity bits for address fault detection. This segmentation allows each parity system to be optimized for its specific purpose, with address parity bits specifically designed to detect address line faults rather than being diluted by combined data-address parity computation.
Solution Approach 2:
The patent introduces separate address parity bits as an intermediary mechanism that specifically monitors address line integrity. These address parity bits act as a dedicated mediator between the address input and error detection, providing specialized protection for address faults without interfering with data parity functionality.
2Reliability
If standard parity protection is used on write data, then data integrity is improved, but Write Enable (WE) signal fault detection deteriorates (stuck-inactive and stuck-active faults undetected)
Solution Approach 1:
The patent implements preliminary action by capturing and storing the state of the WE signal at the moment of the write operation into dedicated WE status flip-flops. This preliminary capture occurs before any potential fault manifestation, allowing subsequent comparison to detect stuck-inactive or stuck-active WE faults that would otherwise remain undetected by standard data parity checking.
Solution Approach 2:
The patent establishes a feedback mechanism where the captured WE signal states are continuously compared against expected values during read operations. This feedback loop enables the system to detect and report WE signal faults, providing closed-loop monitoring that enhances WE signal reliability without compromising data integrity protection.
Data Source
AI summary
A memory system that splits a data width (W) into N separate memories each of narrower width W/N is described. To protect a write enable (WE) signal, the WE signal is toggled and then stored in each of the N memories. A fault on the WE signal to any of the N memories results in its stored write detection bit being different from the write detection bits stored in the other N memories. This condition can then be detected upon any subsequent read by checking whether the write detection bits are equal. The memory system can also protect the address and control signals by generating parity bits that are stored in the N memories.