Memory Control Circuit Pulse Pattern Detection for Embedded Storage Debugging
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Solution Overview
Problem
Debugging embedded storage devices soldered to electronic devices is challenging due to data errors and loss caused by high temperature soldering and desoldering processes, which makes it difficult to correctly identify and correct anomalies without desoldering the devices.
Innovation Solution
A memory control circuit unit with a pulse pattern detecting circuit that disables the reset function of the memory storage device when a specific pulse pattern is recognized, allowing for access and debug analysis without desoldering, using a reset pin to enable two-way data transmission and prevent data loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the eMMCs are soldered to the circuit boards through high temperature tin furnace process, then the electronic products can be mass produced, but the charges stored in the memory cells may be affected causing data errors or loss
Solution Approach 1:
The patent applies preliminary action by performing debug analysis on eMMCs before they are soldered to the circuit boards. The method includes reading data from the eMMC, verifying data integrity, and identifying anomalies before the high-temperature soldering process occurs, thus preventing data loss that would otherwise require desoldering for correction
Solution Approach 2:
The patent uses an intermediary debugging interface that allows communication with the eMMC through the reset pin without requiring physical access to the eMMC after soldering. This intermediary mechanism enables data verification and anomaly detection while the eMMC is in its mounted state, avoiding the need to desolder for debugging
2Ease of manufacture
If the eMMCs are soldered to the electronic products, then the product can be assembled, but the eMMC becomes inaccessible for debug analysis and parameter correction
Solution Approach 1:
The patent makes the reset pin serve multiple functions: it acts as a standard reset signal input during normal operation, and simultaneously serves as a debugging interface for data transmission between the host system and the eMMC. This multi-functionality allows the eMMC to remain accessible for debug analysis even after being soldered to the circuit board
Solution Approach 2:
The patent implements a feedback mechanism where the host system transmits commands through the reset pin and receives responses from the eMMC, enabling real-time monitoring and correction of eMMC status. This feedback loop allows continuous verification of data integrity and anomaly detection without requiring physical access to the eMMC
3Measurement precision
If multiple high temperature soldering and desoldering processes are performed for debug analysis, then anomalies can be detected, but data stored in the eMMCs becomes erroneous or lost
Solution Approach 1:
The patent performs all necessary debug analysis, data verification, and anomaly detection before the eMMC undergoes high-temperature soldering. By reading and verifying data in advance, the system identifies potential issues without requiring subsequent desoldering operations that would expose the eMMC to thermal stress and data loss
Solution Approach 2:
The patent applies preliminary anti-action by preventing the harmful effect of high-temperature exposure on stored data. Through pre-soldering verification and the use of the reset pin for ongoing monitoring, the system counteracts the potential for thermal damage before it occurs, eliminating the need for repeated soldering and desoldering cycles
Data Source
AI summary
A memory control circuit unit, a memory storage device and a data transmitting method are provided. The memory storage device coupled to a first host system includes a reset pin. The memory control circuit unit of the memory storage device includes a pulse pattern detector. The reset pin is coupled to a second host system and is configured to receive a first pulse signal from the second host system. The pulse pattern detector is coupled to the reset pin, and is configured to determine whether the first pulse signal is conformed to a first predetermined serial pulse pattern or not. If the first pulse signal is conformed to the first predetermined serial pulse pattern, the memory control circuit unit is configured to disable a reset function of the memory storage device.