Memory Control Circuit Read-Ahead for Frame Delay Reduction
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Solution Overview
Problem
Conventional memory control circuits in image processing apparatuses, such as liquid crystal display devices, face challenges with long delay periods before starting to output data from frame memories, leading to increased size requirements for shift registers and difficulties in timing adjustments due to the inherent latency of SDRAM access.
Innovation Solution
The proposed solution involves generating and supplying address and control signals to frame memories to read past data before receiving data for the next frame, utilizing a synchronizing signal to initiate address generation and control operations, and storing read-ahead data in FIFOs to synchronize the output with incoming data, thereby reducing the delay time and shift register size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional SDRAM access timing is used, then data can be read from frame memory, but the delay period before outputting past data becomes long
Solution Approach 1:
The patent applies preliminary action by initiating the row address specification and data read operation from frame memory before the current frame data input is complete. The memory control circuit starts reading past data at timing T1, before the current frame data input ends at timing T2, thereby overlapping the read operation with the data input period and reducing the overall delay period.
2Loss of time
If SDRAM latency is reduced, then data output delay is shortened, but timing synchronization becomes more difficult
Solution Approach 1:
The patent uses feedback by monitoring the actual timing of data read completion from frame memory and dynamically adjusting the timing of address signal generation and control signal output. The memory control circuit receives feedback about data availability and synchronizes subsequent operations accordingly, maintaining precise timing coordination while achieving shorter delay periods.
3Productivity
If data reading is started earlier, then output delay is reduced, but data input completion may be interrupted
Solution Approach 1:
The patent segments the data processing operations by separating the read operation into distinct phases: the row address specification phase initiated at T1, and the column address specification phase completed at T3. This segmentation allows the read operation to proceed in stages without interfering with the current frame data input, ensuring both early initiation and complete data transfer.
Data Source
AI summary
Various exemplary embodiments provide methods of controlling frame memory, memory control circuits, and image processing apparatuses including the memory control circuits. Data representing values of pixels constituting each of a plurality of frames are received in an order of the frames, and data representing values of pixels constituting a previous frame are read from the frame memory and data representing values of pixels constituting a next frame are written to the frame memory. By reading first data representing values of a portion of the pixels constituting the previous frame from the frame memory before receiving of data representing values of pixels constituting the next frame starts, a delay time before starting to output data representing values of pixels of the previous frame can be shortened.