Memory Control Circuit Unit Read Voltage Adjustment

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Solution Overview

Problem

In rewritable non-volatile memory modules, reading errors occur due to differences in physical blocks being open or closed, complicating data correction, especially when reading from blocks with varying numbers of physical programming units in erased status.

Innovation Solution

A memory control method that distinguishes between different types of physical erasing units by sending specific operation command sequences based on electronic configurations, adjusting read voltages and currents to improve data accuracy.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a single read operation command sequence is used for all physical erasing units, then the device complexity is reduced, but reading accuracy deteriorates due to differences in open and closed blocks

Engineering Contradiction:
Improveread operation command sequenceVSAvoidreading accuracy
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

The patent segments the read operation by dividing physical erasing units into two types (open blocks and closed blocks) and assigning different read operation command sequences to each type. This segmentation allows the system to tailor the read operation to the specific characteristics of each block type, thereby improving reading accuracy without significantly increasing overall device complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic read operation adjustment by determining the type of physical erasing unit and selectively applying different read operation command sequences. This dynamic approach allows the system to adapt the read operation parameters based on the actual state of the memory blocks, optimizing reading accuracy for both open and closed blocks.

Inventive Principle:
Principle #15Dynamics

2Measurement precision

If different electronic configurations are used for different physical erasing unit types, then reading accuracy is improved, but the device complexity increases

Engineering Contradiction:
Improvedata reading accuracyVSAvoidelectronic configuration
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by determining the type of physical erasing unit before executing the read operation. The controller identifies whether a block is open or closed and pre-selects the appropriate read operation command sequence and electronic configuration, ensuring optimal reading conditions are established in advance for each block type.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent changes electrical parameters (such as read voltage levels, timing parameters, or signal configurations) based on the type of physical erasing unit. By adjusting these electrical parameters according to whether the block is open or closed, the system optimizes the read operation for each block type, improving data reading accuracy while managing complexity through parameterization.

Inventive Principle:
Principle #35Parameter changes

3Measurement precision

If read operations are adjusted based on physical erasing unit type, then data retrieval precision is improved, but the operation time increases

Engineering Contradiction:
Improvedata retrieval precisionVSAvoidoperation time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent performs the determination of physical erasing unit type and selection of appropriate read operation command sequences in advance, before the actual data read operation begins. This preliminary classification and configuration selection minimizes the time penalty during the actual read operation, as the optimal parameters are already determined and ready for execution.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11829644B2Memory control method, memory storage device, and memory control circuit unit
Publication Date: 2023.11.28 PHISON ELECTRONICS
  • US11829644B2 patent drawing
  • US11829644B2 patent drawing
  • US11829644B2 patent drawing

AI summary

A memory control method, a memory storage device, and a memory control circuit unit are provided. The memory control method includes: receiving a read command from a host system; in response to a first physical erasing unit being a first type physical unit, sending a first operation command sequence to instruct a rewritable non-volatile memory module to read a first physical programming unit based on a first electronic configuration; and in response to the first physical erasing unit being a second type physical unit, sending a second operation command sequence to instruct the rewritable non-volatile memory module to read the first physical programming unit based on a second electronic configuration. The first electronic configuration is different from the second electronic configuration.