Non-volatile Memory Control Information Reading Speed
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Solution Overview
Problem
In non-volatile memory devices, the increasing quantity of control information such as write protect information and trimming information leads to longer reading times due to insufficient driving capacity of memory cells, and applying higher biases for faster reading can stress the memory cells and complicate circuit configurations.
Innovation Solution
Allocating a predetermined number of memory cells per bit of control information and reading out identical-bit data simultaneously from these cells to enhance driving capacity without requiring excessive biases or additional bias generation circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If control information is stored in the memory cell array region, then the quantity of information is stored in minimum required occupied area, but the reading route becomes very long and wiring load increases
Solution Approach 1:
The memory cell array is divided into normal-data storing regions and control-information storing regions, with control information stored in dedicated memory cells. This segmentation allows control information to be stored in a compact region close to the control circuit, reducing the reading route length while maintaining efficient space utilization.
2Speed
If bias voltage is increased to raise driving capacity for faster reading, then reading speed is improved, but excessive stress is applied to memory cells and device reliability deteriorates
Solution Approach 1:
Multiple memory cells storing identical-bit data are merged into a parallel reading structure. The combined output of these cells provides sufficient driving capacity for fast reading without requiring excessive bias voltage, thus maintaining device reliability while achieving high reading speed.
3Power
If larger bias than normal use is applied to memory cell, then driving capacity is raised for faster reading, but circuit configuration becomes complicated with bias generating circuit needed
Solution Approach 1:
Multiple memory cells are combined in parallel to provide increased driving capacity using normal bias voltage. This merging approach eliminates the need for complex bias generating circuits while achieving the required power output for fast reading operations.
4Area of stationary object
If reading route is made long to store control information in memory cell array, then space is efficiently utilized, but reading time of control information becomes longer
Solution Approach 1:
The memory array is segmented into dedicated control-information storing regions located adjacent to the control circuit. This segmentation creates a short reading route for control information, reducing reading time while efficiently utilizing memory space through organized regional allocation.
Data Source
AI summary
In a memory cell array, aside from a normal-data storing region, a control-information storing region is also allocated, and the control-information storing region is composed of a predetermined number of control-information storing memory cells in each bit of control information, and same bit data is stored in the predetermined number of control-information storing memory cells, and the data is read out simultaneously at the time of reading out. When being read-out the control information, since data is read out simultaneously from the predetermined number of memory cells, the driving capacity of reading route when reading out is reinforced. Reading time of control information being read out at the time of turning on the power or initializing after resetting can be shortened, and the operation can be quickly transferred to normal access action.