Memory Control Circuitry Routing Transactions by Address Range
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Solution Overview
Problem
Existing data processing apparatuses struggle to take advantage of performance benefits from different memory interfaces without increasing programming complexity, as they either execute memory access instructions uniformly across all interfaces or require separate instructions for each interface.
Innovation Solution
A data processing apparatus with memory control circuitry that routes memory transactions through different interfaces based on memory address ranges, modifying the execution timing of memory access instructions to optimize performance without needing interface-specific instructions in the instruction set.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If separate memory access instructions are provided for each interface, then the processor core can internally take advantage of performance benefits from different interfaces, but programming complexity significantly increases
Solution Approach 1:
The patent introduces an intermediary mechanism (interface selection logic and timing control circuitry) that automatically routes memory transactions to the appropriate interface based on address ranges and transaction types. This intermediary handles the complexity of interface selection and timing adjustments, allowing the processor to utilize multiple interfaces with different performance characteristics while presenting a unified, simple instruction set to programmers.
Solution Approach 2:
The system dynamically changes execution parameters (timing characteristics, interface selection) based on the memory address being accessed and the type of transaction required. Different address ranges are mapped to different interfaces with optimized timing parameters, allowing the same instruction to be executed with different timing characteristics depending on the target interface, thus achieving performance optimization without increasing programming complexity.
2Device complexity
If uniform memory access instructions are used for all interfaces, then programming complexity remains low, but the processor core cannot take advantage of performance benefits from different interfaces
Solution Approach 1:
The memory address space is segmented into different ranges, each associated with specific interfaces having different performance characteristics. The segmentation allows the system to direct transactions to high-performance interfaces for time-critical operations while using standard interfaces for less demanding operations, thereby utilizing performance benefits without requiring programmers to write different instructions for each interface type.
Solution Approach 2:
The system dynamically selects which interface to use for each memory transaction based on the address range and transaction characteristics. This dynamic selection allows the processor to adaptively utilize the most appropriate interface for each operation, capturing performance benefits from high-speed interfaces when needed while maintaining simple uniform instructions for all memory access operations.
Data Source
AI summary
A data processing apparatus has processing circuitry for executing a memory access instruction in order to generate a memory transaction comprising at least one address transfer specifying a memory address, and at least one associated data transfer specifying data to be accessed at the specified memory address. The apparatus is arranged to route each address transfer and associated data transfer via a first interface when the specified memory address is within a first memory address range, or to route each address transfer and associated data transfer via a second interface when the specified memory address is within a second memory address range and is further configured, when using the first interface, to execute the memory access instruction so as to cause each address transfer and associated data transfer to be presented at the first interface with a first relative timing.