Memory Control Element Safety Interface for Error Detection
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Solution Overview
Problem
Current memory control elements in computer systems face challenges in detecting and correcting multiple errors quickly enough to meet stringent safety requirements, particularly in safety-critical applications, and this can lead to performance degradation and increased error rates due to transient data corruption from factors like cosmic radiation and electromigration.
Innovation Solution
A memory control element with an additional security interface and checking circuit that allows for timely detection and correction of data falsifications, including multiple errors and CRC block errors, while maintaining system performance by checking memory contents at an early stage and initiating a safe state when error thresholds are exceeded, with adjustable error thresholds and check periods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error detection and correction mechanisms are added to meet safety requirements, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent combines the security interface with the existing memory control element architecture by integrating the checking circuit into the memory control element itself. The security interface is merged with the user interface and control circuit, sharing common resources such as the arbiter and data bus, thereby achieving high reliability without proportionally increasing device complexity.
Solution Approach 2:
The memory control element is designed to perform multiple functions: it serves as both the original memory control interface and the security checking interface. The same control circuit and arbiter handle both user access and security checks, making the system multi-functional and reducing the need for separate dedicated hardware for error detection.
2Reliability
If checking circuit is added to detect errors timely, then reliability is improved, but productivity decreases
Solution Approach 1:
The checking circuit performs error detection periodically rather than continuously. The security interface checks memory contents at scheduled intervals during system operation, allowing the system to maintain productivity while still detecting errors timely. The periodic checking ensures safety without requiring constant interruption of data processing.
Solution Approach 2:
The memory control element maintains continuous operation for data processing while the security checks are integrated into the operational flow. The arbiter manages both user requests and security checks, ensuring that useful data processing actions continue without complete interruption, thus maintaining productivity while improving reliability.
3Reliability
If error checking is performed frequently, then reliability is improved, but loss of time increases
Solution Approach 1:
The checking circuit is configured with adjustable check periods that can be dynamically optimized. The system can adapt the frequency of error checking based on operational requirements, ensuring that reliability is improved through timely checks while minimizing time loss. The check period can be adjusted to balance between detection timeliness and system throughput.
4Device complexity
If integration of functionalities is increased, then device complexity is reduced, but reliability deteriorates
Solution Approach 1:
The patent introduces a dedicated checking circuit as an intermediary between the integrated memory control element and the data processing units. This checking circuit acts as a mediator that detects data corruption caused by integration challenges, such as transient errors from cosmic radiation or electromigration, thereby maintaining reliability even as integration increases.
Data Source
AI summary
The invention relates to a memory control element (MC) which has, on a first side (1), at least one user interface (UP1,..., UPn) with an associated actuation circuit (UA1,..., UAn) and, on a second side (2), an interface (MPH) with protocol handling for connection of a memory element (S). The memory control element (MC) also comprises a digital circuit (AR) for allocating access resources, a so-called arbiter. The memory element (MC) is also additionally provided with a safety interface (SP) and an associated checking circuit (SA) which is designed to check data for corruption and faults and, in the event of an adjustable fault threshold being exceeded, initiate a system change to a safe state. The invention also relates to a method for configuring the memory control element (MC) according to the invention, in which method a duration of the checking of the data is set as a setpoint value in the safety interface (SP) and the associated checking circuit (SA) or is derived from estimates of an application behaviour or on the basis of empirical tests. The predefined or derived duration is then used to ascertain a suitable arbiter priority for the safety interface (SP) and the associated checking circuit (SA).