Memory Device Control Memory Segmentation for Parallel Access

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Solution Overview

Problem

Existing memory devices face inefficiencies in utilizing storage space and performing parallel operations due to bottlenecks in control memory access, particularly when multiple independent control logic units need to access shared control memories.

Innovation Solution

A memory device architecture that includes multiple planes with independent control logic and a control memory configuration featuring a common memory accessible by all control logic units and temporary storage areas, allowing parallel access and minimizing storage space usage by storing control codes in temporary storage when not in use.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple independent control logic units access a shared control memory, then the device can perform parallel operations on multiple planes, but access bottlenecks occur reducing operational speed

Engineering Contradiction:

Improveparallel operation capabilityVSAvoidcontrol memory access speed

Core Design Contradiction:

ProductivityVSSpeed

Solution Approach 1:

The control memory is segmented into a common memory region (accessible by all control logic units) and plane-specific memory regions (dedicated to each plane's control logic). This segmentation allows simultaneous access without conflicts by directing different types of access requests to appropriate regions.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

A memory management unit acts as an intermediary between the multiple control logic units and the control memory. It manages access requests, determines whether to access the common memory or temporary storage, and coordinates parallel accesses to prevent bottlenecks.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Quantity of substance

If control codes are stored in common control memory for all planes, then storage space is utilized, but access bottlenecks occur when multiple control logic units need simultaneous access

Engineering Contradiction:

Improvestorage space utilizationVSAvoidparallel access efficiency

Core Design Contradiction:

Quantity of substanceVSProductivity

Solution Approach 1:

The control memory is divided into a common memory region for storing control codes that can be shared across planes, and plane-specific temporary storage regions. This allows efficient parallel access by directing plane-specific operations to temporary storage while maintaining storage space utilization through the common region.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Control codes are pre-loaded into plane-specific temporary storage regions before parallel operations begin. This preliminary action ensures that when multiple control logic units need to access control codes simultaneously, they can do so from their dedicated temporary storage without causing access bottlenecks.

Inventive Principle:

Principle #10Preliminary action

3Speed

If separate control memories are allocated for each plane, then parallel access is enabled, but storage space utilization decreases

Engineering Contradiction:

Improveparallel access speedVSAvoidstorage space utilization

Core Design Contradiction:

SpeedVSQuantity of substance

Solution Approach 1:

The control memory architecture is segmented into a shared common memory region and dedicated plane-specific temporary storage regions. This hybrid approach enables parallel access for plane-specific operations while maintaining high storage space utilization through the shared common region.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The common memory region serves multiple functions: storing control codes for all planes, acting as a shared cache, and providing backup storage. This multi-functionality allows efficient storage space utilization while supporting parallel operations through the plane-specific temporary storage regions.

Inventive Principle:

Principle #6Universality (Multi-functionality)

4Speed

If control codes are cached in temporary storage for fast access, then access speed improves, but storage space is consumed

Engineering Contradiction:

Improvecontrol code access speedVSAvoidtemporary storage space

Core Design Contradiction:

SpeedVSQuantity of substance

Solution Approach 1:

Each plane's control logic unit has its own dedicated temporary storage region with optimized characteristics for that plane's specific access patterns. This local optimization allows fast access for plane-specific operations while the common memory region handles shared control codes, balancing speed and storage space consumption.

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS11392326B2Memory device and method of operating the memory device

Publication Date: 2022.07.19 MIMIRIP LLC

AI summary

Provided herein may be a memory device and a method of operating the same. The memory device may include a memory cell array including multiple planes, a peripheral circuit configured to perform an operation on the multiple planes, a control memory configured to store control codes for controlling the peripheral circuit, and a plurality of independent control logic configured to, when a command corresponding to each of the planes is received from a memory controller, control the peripheral circuit with reference to a control code corresponding to the command in response to the command. The control memory includes a common memory configured to be accessible in common by the plurality of independent control logic, and a temporary storage including areas respectively corresponding to the planes.