Nonvolatile Memory Pin Reduction via Control Signal Encoding
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Solution Overview
Problem
Current semiconductor memory devices face challenges in efficiently managing and synchronizing command, address, and data signals between memory controllers and devices, particularly in nonvolatile memory systems, which affects operational modes and pin count, leading to increased costs and power consumption.
Innovation Solution
The implementation of a memory controller and memory device system using first and second control pins to indicate signal states and a data strobe signal for synchronization, allowing the system to operate in reduced pin modes and normal modes, thereby reducing the number of control signals and pins required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple separate control signals are used to manage command, address, and data states, then signal clarity and reliability are improved, but the number of control pins increases
Solution Approach 1:
The patent combines multiple control functions into a single control pin by encoding different control states (command state, address state, data input state, data output state) as different voltage levels or logic states on one shared control line. This merging approach maintains clear signal differentiation while reducing the total number of control pins required in the memory system.
Solution Approach 2:
The control pin is designed to serve multiple functions by dynamically changing its signal characteristics to indicate different operational states. A single control pin universally manages command transmission, address transmission, data input, and data output operations, eliminating the need for separate dedicated control lines for each function.
2Manufacturing precision
If more control pins are used to manage signal states, then operational control precision is improved, but manufacturing cost increases
Solution Approach 1:
By merging multiple control functions into a single control pin that uses encoded voltage levels or logic states to differentiate between command, address, and data operations, the patent reduces the total pin count required. This directly lowers manufacturing costs associated with fewer I/O pins while maintaining precise operational control through the encoded signal states.
3Adaptability or versatility
If more pins are required for memory operations, then signal management capability is improved, but power consumption increases
Solution Approach 1:
The patent merges multiple control functions into a single control pin that dynamically encodes different operational states. This reduction in the number of active control pins directly decreases the total power consumption of the memory interface, as fewer pins require drive circuits, signal buffering, and associated power management, while the encoding mechanism maintains full signal management capability.
Data Source
AI summary
A nonvolatile memory system is provided. The memory system includes a nonvolatile memory device and a memory controller. The memory controller transmits first to fourth control signals to the nonvolatile memory device, sends a command, an address, and input data via a data bus, and receives output data via the data bus. The nonvolatile memory device receives the first to fourth control signals, and recognizes signals received via the data bus at a rising edge or a falling edge of the fourth control signal, as one of the command, the address, and the input data in response to the first to third control signals, and transfers the output data to the memory controller via the data bus based on the fourth control signal.