Memory Control Circuit Staggering Refresh and Calibration Commands
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Solution Overview
Problem
DDR-SDRAMs face issues with accepting access commands during calibration and refresh operations, leading to prolonged waiting times due to the sequential nature of these commands, with existing technologies lacking effective timing control to prevent such succession.
Innovation Solution
A memory control technique that employs suppression periods and counters to stagger the issuance of refresh and calibration commands, ensuring they are not issued successively, allowing for programmable restraint periods and prioritizing access requests.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If refresh and calibration commands are issued sequentially without timing control, then both operations are performed, but access speed is reduced due to successive command issues
Solution Approach 1:
The patent implements periodic timing control by issuing refresh and calibration commands at predetermined intervals rather than continuously or randomly. The control circuit monitors timing parameters and ensures that these maintenance commands are spaced appropriately to avoid succession, thereby maintaining access speed while ensuring reliable periodic execution of refresh and calibration operations.
2Reliability
If refresh and calibration commands are issued in succession, then both operations are completed, but waiting time for access commands increases
Solution Approach 1:
The control circuit performs preliminary timing analysis before issuing refresh or calibration commands. By monitoring the timing parameters and predicting when maintenance commands will be needed, the system can schedule them in advance at optimal intervals, preventing successive issuance and reducing waiting time for access commands while ensuring maintenance operations are completed.
3Ease of operation
If no timing control is implemented for refresh and calibration commands, then command issuance is simple, but successive commands cause performance degradation
Solution Approach 1:
The memory control circuit incorporates self-service timing control by automatically monitoring its own command issuance timing and regulating when refresh and calibration commands are sent. This internal self-regulation mechanism maintains operational simplicity while preventing performance degradation, as the circuit autonomously manages the timing intervals without requiring external control or complex scheduling logic.
Data Source
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AI summary
Provided is a memory control technique for avoiding that the issue of a refresh command and the issue of a calibration command are arranged in succession. The memory control circuit issues a refresh command to make a request for a refresh operation based on a set refresh cycle, and issues a calibration command to make a request for a calibrating operation based on a set calibration cycle, for which the control function of suppressing the issue of the calibration command only for a given time after the issue of the refresh command, and suppressing the issue of the refresh command only for a given time after the issue of the calibration command is adopted.