Memory Control Unit Descriptor Fetching for Nonvolatile Memory
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Solution Overview
Problem
Current data storage apparatuses using memory devices face inefficiencies in generating control signals due to high memory capacity requirements for instructions, which can limit their performance and flexibility in controlling nonvolatile memory devices.
Innovation Solution
A memory control unit is introduced, comprising a descriptor fetch block, an instruction fetch block, and a memory instruction generation block, which fetches descriptors and instruction sets from volatile and instruction memories, respectively, to generate control signals for nonvolatile memory devices, reducing memory capacity needs by using index information for address retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional memory control methods are used to generate control signals for nonvolatile memory devices, then the control signals can be generated, but the memory capacity required for storing instructions becomes excessively large
Solution Approach 1:
The patent segments the instruction memory into multiple banks (first instruction bank, second instruction bank, etc.) and divides the instruction fetch operation into parallel paths. Each bank can be accessed simultaneously through different address information, enabling concurrent retrieval of multiple instructions and reducing the total memory capacity needed while maintaining generation efficiency.
Solution Approach 2:
The patent implements a nested structure where descriptor information (including address information for instruction memory) is stored in volatile memory, which is then used to access the instruction memory. This nested arrangement allows compact storage of control data and efficient retrieval without requiring large dedicated instruction memory capacity.
2Reliability
If large memory capacity is allocated for instruction storage, then all necessary instructions can be stored, but the overall system complexity and resource consumption increase
Solution Approach 1:
The patent employs dynamic address generation where the address information for instruction memory is not fixed but is instead generated based on descriptor information that can be modified during operation. This dynamic approach allows the same memory structure to adapt to different instruction retrieval needs without requiring additional memory capacity, thereby reducing system complexity while maintaining reliability.
3Quantity of substance
If index information is used to obtain address information from instruction memory, then memory capacity is reduced, but the control logic complexity increases
Solution Approach 1:
The patent introduces descriptor information as an intermediary structure that contains address information for the instruction memory. This descriptor acts as a mediator between the volatile memory and the instruction memory banks, simplifying the control logic by providing a standardized interface for address generation while enabling efficient memory capacity utilization through indexed access.
Data Source
AI summary
The memory control unit includes a descriptor fetch block suitable for fetching a descriptor from a volatile memory; an instruction fetch block suitable for fetching an instruction set from an instruction memory through an address information, wherein the instruction fetch block obtains the address information from the instruction memory through an index information included in the fetched descriptor; and a memory instruction generation block suitable for generating a memory instruction by combining a descriptor parameter value included in the fetched descriptor to the fetched instruction set.