Memory Control Unit Descriptor-Based Signal Generation

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Solution Overview

Problem

Existing data storage devices face challenges in efficiently generating control signals for memory devices, which affects the operation speed and performance of these devices.

Innovation Solution

A memory control unit is designed to efficiently generate control signals by fetching an instruction set from an instruction memory based on a descriptor, using a descriptor fetch block, instruction fetch block, and signal generation block, along with a DMA block and descriptor queue to manage data and instructions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a memory control unit generates control signals for a memory device, then the operation speed of the data storage device increases, but the complexity of the control unit increases

Engineering Contradiction:

Improveoperation speedVSAvoidcontrol unit complexity

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The control unit is divided into multiple functional blocks including a descriptor fetch block, instruction fetch block, instruction push block, and signal generation block. Each block performs a specific function in the control signal generation process, allowing the system to achieve high operation speed through specialized processing while managing complexity through functional decomposition.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The descriptor fetch block reads descriptors from working memory in advance, and the instruction fetch block fetches instruction sets from instruction memory based on the descriptors before actual memory operations are needed. This preliminary fetching and buffering of control information enables faster execution without proportionally increasing control unit complexity.

Inventive Principle:

Principle #10Preliminary action

2Productivity

If control signals are generated efficiently using descriptor-based instruction sets, then productivity increases, but device complexity increases

Engineering Contradiction:

Improvecontrol signal generation efficiencyVSAvoidmemory control unit complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The control logic is extracted into separate functional blocks (descriptor fetch block, instruction fetch block, instruction push block, signal generation block) rather than being implemented as a monolithic control unit. This extraction allows efficient control signal generation through specialized processing while managing complexity through modular design.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The instruction memory and descriptor structure provide a universal framework that can handle various memory operations (read, write, erase, etc.) through a common control mechanism. The instruction push block and signal generation block work together to translate generic instruction sets into specific control signals, achieving productivity through multi-functional processing without proportionally increasing complexity.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS9652403B2Memory control unit and data storage device including the same

Publication Date: 2017.05.16 SK HYNIX INC

AI summary

A data storage device includes a storage memory device, a control unit suitable for generating a descriptor, which describes a work for controlling the storage memory device, and storing the descriptor in a working memory, and a memory control unit suitable for generating control signals for the storage memory device by fetching an instruction set from an instruction memory based on the descriptor.