Memory Control Unit ECC Block Pre-encoding for Operation Speed

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Solution Overview

Problem

Current data storage devices face limitations in operation speed due to sequential execution of data encoding and control signal generation, which can hinder performance in ubiquitous computing environments where rapid data access is essential.

Innovation Solution

Incorporating an error correction code (ECC) block that operates prior to the signal generation block, allowing for ECC encoding to be completed before control signals are generated, and utilizing a descriptor processing block to manage and instruct the ECC and signal generation processes, ensuring efficient data handling and control signal generation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If ECC encoding is performed sequentially before control signal generation, then data reliability is improved, but operation speed deteriorates

Engineering Contradiction:
Improvedata reliabilityVSAvoidoperation speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The patent applies preliminary action by performing ECC encoding in advance during the data input phase, so that encoding is completed before the control signal generation phase begins. This allows the encoded data to be ready when needed, improving operation speed while maintaining data reliability through proper error correction encoding.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent segments the data processing into distinct phases: data input phase, control signal generation phase, and data output phase. By separating ECC encoding into its own preliminary step within the input phase, the system avoids sequential bottlenecks and improves overall operation speed while ensuring reliability.

Inventive Principle:
Principle #1Segmentation

2Speed

If multiple processing blocks operate in parallel, then operation speed is improved, but device complexity increases

Engineering Contradiction:
Improveoperation speedVSAvoiddevice complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent divides the control unit into three independent processing blocks: data input block, control signal generation block, and data output block. Each block operates independently and can process data in parallel, improving operation speed while managing complexity through clear functional separation and standardized interfaces between blocks.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS9501351B2Memory control unit and data storage device including the same
Publication Date: 2016.11.22 SK HYNIX INC
  • US9501351B2 patent drawing
  • US9501351B2 patent drawing
  • US9501351B2 patent drawing

AI summary

A data storage device includes a storage memory device; a signal generation block suitable for generating control signals to be provided to the storage memory device; and an error correction code (ECC) block suitable for ECC-encoding data to be stored in the storage memory device, wherein the ECC block operates before the signal generation block.