Semiconductor Memory Control Logic for Erase Voltage Optimization
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Solution Overview
Problem
Current semiconductor memory devices face inefficiencies in erase operations due to the lack of effective control over voltage levels during erase operations, particularly when dealing with memory blocks sharing common source and bit lines, which affects the erase speed and reliability.
Innovation Solution
The semiconductor memory device incorporates a control logic that adjusts the voltage levels of the source and drain select lines based on the program and erase status of unselected memory blocks, allowing for differential or equal voltage application during erase operations, thereby optimizing the erase process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If voltage levels are not controlled during erase operations in memory blocks sharing common source and bit lines, then the device complexity is reduced, but the erase speed and reliability deteriorate
Solution Approach 1:
The control logic determines the program/erase status of unselected memory blocks before performing the erase operation on the selected memory block. This preliminary status check allows the system to pre-determine the appropriate voltage levels to apply to select lines, ensuring reliable erase operation while avoiding the need for complex real-time voltage adjustment mechanisms.
Solution Approach 2:
The patent implements dynamic voltage control where the voltage levels applied to source and drain select lines are adjusted based on the determined status of unselected memory blocks. The control logic applies different voltage combinations (e.g., different between source and drain select lines when unselected blocks are in program status, equal voltages when in erase status) to optimize erase reliability for the selected block while considering the state of shared resources.
2Productivity
If voltage levels are adjusted based on unselected memory block status, then the erase speed is improved, but the device complexity increases
Solution Approach 1:
The control logic determines the program/erase status of unselected memory blocks before performing the erase operation. This preliminary determination enables the system to quickly select the appropriate voltage scheme without requiring complex real-time adjustments during the erase process, thereby improving erase speed while keeping the control mechanism relatively simple.
Solution Approach 2:
The patent changes voltage parameters (levels and differentials) based on the status of unselected memory blocks. By implementing a control logic that selects from a finite set of voltage configurations rather than continuously adjusting voltages, the system achieves fast erase operations with manageable device complexity.
3Productivity
If differential voltage is applied to source and drain select lines, then the erase efficiency is improved, but the manufacturing precision requirements increase
Solution Approach 1:
The control logic implements discrete voltage level changes based on unselected block status. Rather than requiring high-precision continuous voltage control, the system uses predefined voltage levels and differential configurations, which are easier to manufacture and maintain while still achieving improved erase efficiency through selective voltage application.
Data Source
AI summary
Provided herein may be a semiconductor memory device that may include a plurality of memory blocks configured to share bit lines and a common source line, a voltage generation circuit configured to apply an erase voltage to the common source line, and operation voltages to word lines and select lines of the plurality of memory blocks during an erase operation, a read and write circuit configured to check a program and erase status of an unselected memory block of the plurality of memory blocks during the erase operation, and a control logic configured to control the voltage generation circuit so that the operation voltages applied to select lines of a selected memory block are controlled in accordance with a result of checking the program and erase status of the unselected memory block during the erase operation.