Memory Controller Abort Command Queue Segmentation
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Solution Overview
Problem
Current memory controllers often execute target commands before abort commands, leading to data loss and reduced efficiency due to the inability to timely abort target commands, affecting the reliability and performance of memory systems.
Innovation Solution
A memory controller with a host interface circuit and processor that detects and prioritizes abort commands, identifying target commands through unique identifiers and queue locations to ensure timely execution of abort commands, thereby reducing data loss and improving system efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the memory controller executes commands in the order they are received, then the command execution is simple and straightforward, but the target command cannot be aborted timely leading to data loss
Solution Approach 1:
The patent applies preliminary action by introducing a dedicated abort command queue that is prepared in advance to store abort commands. This allows the memory controller to receive and prepare abort commands before they are needed, enabling timely interruption of target commands without disrupting the normal command execution flow. The abort command queue is set up separately from the main command queue, allowing abort operations to be pre-positioned and executed immediately when needed.
Solution Approach 2:
The patent segments the command processing system into multiple independent queues: a normal command queue for regular operations and a separate abort command queue for interruption operations. This segmentation allows abort commands to be processed independently from normal commands, enabling the memory controller to handle both types of operations simultaneously without interference. The segmentation is implemented through separate queue structures that can be managed independently, improving both reliability and complexity management.
2Reliability
If the memory controller prioritizes abort commands over target commands, then data loss is reduced, but the command processing complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-positioning abort commands in a dedicated abort command queue before they are needed to interrupt target commands. This allows the memory controller to retrieve and execute abort commands immediately when needed, without delaying normal command processing. The abort commands are prepared in advance in their own queue, enabling rapid prioritization without disrupting the overall command processing flow or reducing productivity.
Solution Approach 2:
The patent segments command processing into separate queues, allowing abort commands to be prioritized independently from normal commands. The abort command queue is separate from the main command queue, enabling the memory controller to handle abort operations without blocking normal command processing. This segmentation maintains productivity by allowing both types of commands to be processed in parallel through their respective queues.
3Device complexity
If the memory controller uses a single command queue for all commands, then the structure is simple, but abort commands cannot be executed timely causing data loss
Solution Approach 1:
The patent segments the single command queue into two separate queues: a normal command queue for regular operations and an abort command queue for interruption operations. This segmentation enables the memory controller to handle abort commands independently, allowing timely execution of abort operations without disrupting normal command processing. The separate queues provide dedicated pathways for different command types, improving reliability while maintaining manageable complexity through clear functional separation.
Solution Approach 2:
The patent applies preliminary action by establishing the abort command queue in advance as a separate structure ready to receive and process abort commands. This pre-prepared structure allows the memory controller to immediately process abort commands when needed, without requiring complex real-time queue management. The abort queue is set up beforehand with the appropriate data structures and processing logic, enabling reliable command abortion capability without adding excessive complexity during operation.
Data Source
AI summary
Examples of the present disclosure provide memory controllers and operation methods thereof, memory systems, and electronic devices. An example memory controller includes a host interface circuit configured to: obtain commands from a host and queue the commands in a command queue; and a processor coupled to the host interface circuit and configured to: detect whether there is an abort command in the command queue, wherein the abort command is to instruct to abort a target command in the command queue; and abort the target command in response to the abort command.