Memory Controller Adaptive Bit Error Correction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current memory devices, particularly MRAMs, face challenges in maintaining data correctness due to fluctuations in thermal stability, leading to bit errors that are difficult to correct through periodic readout and writeback, as traditional error-correcting codes are inadequate for addressing multibit errors.
Innovation Solution
Implementing a memory device with a memory controller that uses an error-correcting code to periodically read out bit sequences stored as code words, correct errors, and write back corrected sequences, while also varying the frequency of checks based on reliability information derived from physical parameters like thermal stability, to efficiently manage bit error correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If periodic readout and writeback operations are performed to correct bit errors, then data correctness is improved, but time and energy consumption increase
Solution Approach 1:
The patent applies local quality by differentiating memory cells into first memory cells with lower thermal stability (higher error probability) and second memory cells with higher thermal stability (lower error probability). The memory controller checks first memory cells more frequently than second memory cells, optimizing the balance between reliability and time/energy consumption by applying stricter correction protocols only where needed.
2Reliability
If traditional error-correcting codes are used, then simple bit errors can be corrected, but multibit errors caused by thermal fluctuations cannot be addressed
Solution Approach 1:
The patent implements dynamics by making the error correction strategy adaptive rather than static. The memory controller dynamically adjusts the frequency of readout and writeback operations based on real-time reliability information about each memory cell's thermal stability. This dynamic approach allows the system to handle multibit errors effectively by intensifying correction operations on cells showing degradation, whereas traditional static error-correcting codes cannot adapt to changing thermal conditions.
3Device complexity
If all memory cells are checked with the same frequency, then implementation is simple, but time and energy are wasted on reliable cells
Solution Approach 1:
The patent applies local quality by differentiating memory cells into first memory cells with lower thermal stability (higher error probability) and second memory cells with higher thermal stability (lower error probability). The memory controller checks first memory cells more frequently than second memory cells, optimizing the balance between reliability and time/energy consumption by applying stricter correction protocols only where needed.
4Reliability
If frequent checks are performed on all memory cells, then bit errors are corrected early, but operational efficiency decreases
Solution Approach 1:
The patent applies local quality by differentiating memory cells into first memory cells with lower thermal stability (higher error probability) and second memory cells with higher thermal stability (lower error probability). The memory controller checks first memory cells more frequently than second memory cells, optimizing the balance between reliability and time/energy consumption by applying stricter correction protocols only where needed.
Data Source
AI summary
A memory device includes a memory with first memory cells and second memory cells, which are different from the first memory cells. In the first memory cells there is stored a first bit sequence and in the second memory cells there is stored a second bit sequence. The memory device includes a memory controller, which is configured to check the first bit sequence with a frequency (x1/T) assigned to the first memory cells. The frequency (x1/T) assigned to the first memory cells depends on an item of reliability information for the first memory cells. The memory controller is configured in the case of an error state to correct an erroneous bit of the first bit sequence and to write back at least the corrected bit into the memory. The second bit sequence is checked less often than the first bit sequence on the basis of an item of reliability information for the second memory cells.