Memory Controller Adaptive Test Read for Bad Block Detection
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Solution Overview
Problem
Existing memory systems face inefficiencies in managing memory blocks, particularly in identifying and handling bad blocks, which can impact system performance due to the need for repeated read operations and potential failure bits exceeding a threshold.
Innovation Solution
A memory system that performs a first test read operation on candidate memory blocks, determines a test read method based on a reference value and the number of scanned blocks, and adjusts the method for subsequent test read operations to optimize the number of scanned blocks and word lines, thereby efficiently identifying and managing bad blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a test read operation is performed on all candidate memory blocks to identify bad blocks, then the reliability of data storage is improved, but the time consumption and processing efficiency deteriorate
Solution Approach 1:
The patent applies dynamics by making the test read operation adaptive rather than static. The controller dynamically adjusts the number of word lines to read based on the number of candidate memory blocks identified. When fewer candidate blocks are found, the system reads more word lines from each block to maintain detection accuracy. This dynamic adjustment optimizes the balance between detection reliability and time consumption.
Solution Approach 2:
The patent changes the parameter of word line reading depth based on the number of candidate memory blocks. The controller modifies this parameter dynamically - when the number of candidate blocks decreases, the system increases the number of word lines read from each block. This parameter change allows the system to maintain high detection accuracy while reducing overall time consumption.
2Measurement precision
If the number of word lines read during test read operation is increased, then the detection precision of bad blocks is improved, but the processing efficiency and throughput deteriorate
Solution Approach 1:
The system dynamically adjusts the number of word lines to read based on real-time conditions. When fewer candidate memory blocks are detected, the system automatically increases the number of word lines read from each block to maintain precision. This dynamic behavior ensures high detection precision without unnecessarily reducing throughput.
Solution Approach 2:
The patent implements parameter changes by modifying the word line reading depth based on the number of candidate blocks. This parameter adjustment allows the system to optimize the trade-off between detection precision and processing efficiency, reading more word lines only when necessary to maintain accurate bad block identification.
3Reliability
If test read operations are performed frequently to manage memory block health, then the reliability of the memory system is improved, but the wear on memory blocks and power consumption increase
Solution Approach 1:
The controller dynamically adjusts the extent of test read operations based on the number of candidate memory blocks. When fewer candidate blocks are identified, the system performs more thorough readings from each block rather than repeatedly scanning all blocks. This dynamic approach reduces overall power consumption while maintaining reliable health monitoring.
Solution Approach 2:
The patent applies parameter changes by adjusting the number of word lines read based on the number of candidate blocks. This optimization reduces the total number of read operations required, thereby lowering power consumption while maintaining effective memory block health monitoring and reliability.
Data Source
AI summary
A memory system includes: a memory device; and a controller suitable for performing a first test read operation on a first plurality of candidate memory blocks, determining a test read method of a second test read operation based on a reference value and a first number of the first plurality candidate memory blocks scanned in the first test read operation, and performing the second test read operation on a second plurality of candidate memory blocks based on the determined test read method.