Memory Controller Adaptive Verification for NVM Programming

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Solution Overview

Problem

Current non-volatile memory (NVM) programming processes are inefficient due to the need for extensive verification checks, which increase programming time and overhead, especially when a large number of cells are successfully written, as existing methods do not effectively skip verification checks based on the percentage of passing cells.

Innovation Solution

A memory controller is configured to initiate a program pulse sequence and verify sequence, detecting the percentage of passing cells; if the percentage exceeds a threshold, verification checks are performed; otherwise, they are skipped to reduce programming time, thereby optimizing the programming process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If verification checks are performed for all program pulses, then data writing reliability is improved, but programming time increases

Engineering Contradiction:

Improvedata writing reliabilityVSAvoidprogramming time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent applies partial verification by performing verification checks only on a subset of program pulses rather than all pulses. When a verify pass is detected, subsequent verification checks are skipped, applying verification action only where necessary to maintain reliability while reducing overall programming time.

Inventive Principle:

Principle #16Partial or excessive action

Solution Approach 2:

The programming process is segmented into multiple program pulses with verification checks selectively applied to specific segments. The patent divides the verification process into conditional stages where only certain program pulses require verification, creating distinct segments of verified and unverified operations.

Inventive Principle:

Principle #1Segmentation

2Productivity

If verification checks are skipped to reduce programming time, then programming efficiency is improved, but data writing reliability deteriorates

Engineering Contradiction:

Improveprogramming efficiencyVSAvoiddata writing reliability

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent implements feedback mechanisms where verification results from program pulses influence subsequent verification decisions. When a verify pass is detected, this feedback information is used to skip future verification checks, creating a dynamic system that adapts verification intensity based on actual programming success.

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The verification process transitions from a static all-or-nothing approach to a dynamic conditional approach. The patent makes verification checks adaptive, where the presence or absence of verification in subsequent program pulses depends on the outcome of previous verification attempts, optimizing the balance between reliability and efficiency.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS10049759B2Reducing verification checks when programming a memory device

Publication Date: 2018.08.14 INTEL NDTM US LLC

AI summary

Technology for an apparatus is described. The apparatus can include a memory controller with circuitry configured to initiate a program verify sequence to verify data written to a non-volatile memory (NVM). The program verify sequence can have one or more program verify levels that each correspond to memory cells in the NVM for which written data is being verified. The memory controller can detect an approximate percentage of memory cells for each program verify level in which data is successfully written. The memory controller can determine to skip subsequent program pulse verification checks in one or more program verify levels when the approximate percentage of memory cells in which data is successfully written is less than a defined threshold.