Nonvolatile Memory Controller Address Continuity Segmentation

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Data storage apparatuses using memory devices face degradation in read performance due to mixed storage of sequential and random logical block addresses, leading to inefficient data transfer and storage.

Innovation Solution

A data storage apparatus with a nonvolatile memory device and a controller that separates data storage based on the continuity of logical block addresses, using a first memory region for sequential data and a second region for random data, ensuring efficient storage and migration to maintain read performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If sequential and random logical block addresses are stored together in the same memory region, then storage capacity is maximized, but read performance degrades

Engineering Contradiction:
Improvestorage capacityVSAvoidread performance
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The memory device is divided into two distinct memory regions: a first memory region for storing sequential logical block addresses and a second memory region for storing random logical block addresses. This segmentation allows sequential data to be stored in the faster first region while random data occupies the second region, preventing read performance degradation caused by mixed storage patterns.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different storage characteristics are assigned to different parts of the memory system. The first memory region is optimized for sequential access patterns with faster access speeds, while the second memory region handles random access patterns. This local quality differentiation ensures that each type of data is stored in the most appropriate location, maintaining overall system performance.

Inventive Principle:
Principle #3Local quality

2Device complexity

If data is stored in a single memory region without differentiation, then device complexity is reduced, but data transfer efficiency decreases

Engineering Contradiction:
Improvestorage structureVSAvoiddata transfer efficiency
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The storage structure is segmented into two memory regions with distinct access patterns. The controller includes a sampling unit that analyzes address continuity and a determination unit that decides which memory region to use based on whether addresses are sequential or random, thereby optimizing data transfer efficiency without excessive complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system dynamically determines the storage location based on the continuity of logical block addresses. The sampling unit collects address information and the determination unit dynamically selects the appropriate memory region for each data write operation, allowing the system to adapt to different access patterns in real-time.

Inventive Principle:
Principle #15Dynamics

3Device complexity

If all write requests are processed uniformly, then processing simplicity is maintained, but access speed decreases

Engineering Contradiction:
Improveprocessing logicVSAvoidaccess speed
Core Design Contradiction:
Device complexityVSSpeed

Solution Approach 1:

The processing logic dynamically adapts based on address continuity. The sampling unit collects address information from write requests, and the determination unit dynamically decides whether to write to the first or second memory region based on whether the addresses are sequential or random, optimizing access speed without complex fixed logic.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

Before writing data, the system performs preliminary sampling of address information to determine the access pattern. This preliminary action allows the system to pre-determine the optimal memory region for storage, ensuring fast access speeds from the outset rather than requiring complex real-time switching during data transfer.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10515693B1Data storage apparatus and operating method thereof
Publication Date: 2019.12.24 SK HYNIX INC
  • US10515693B1 patent drawing
  • US10515693B1 patent drawing
  • US10515693B1 patent drawing

AI summary

A data storage apparatus includes a nonvolatile memory device including a first memory region and a second memory region and a controller configured to control a write operation of the nonvolatile memory device. The controller includes a memory configured to store at least one or more write requests and address information for the write requests received from a host apparatus and a processor configured to collect address information corresponding to a preset sampling range among the address information as a first sampling address, determine continuity between the collected address information of the first sampling address, and control the nonvolatile memory device to store data corresponding to all or a portion of the write requests for the address information of the first sampling address in the first memory region based on a determination result.