Dual-Memory Controller for Address Line Error Isolation
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Solution Overview
Problem
Conventional redundant memory systems fail to handle error information in real time, leading to potential system downtime due to unaddressed errors on address lines, which can result in incorrect data usage and system instability.
Innovation Solution
A memory controller that estimates errors on address lines through error checking and generates error data to disable affected memory lines, preventing system downtime by switching data to error data before comparison, thus addressing real-time error handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional redundant memory systems are used with initial diagnosis only, then manufacturing cost and system complexity are reduced, but reliability deteriorates because trouble information cannot be handled in real time leading to system downtime
Solution Approach 1:
The patent performs preliminary error checking and address line error estimation before data access operations. The memory controller estimates whether an address line error has occurred based on ECC check results prior to data retrieval, and pre-switches to error data or disables affected memory lines in advance, preventing system downtime when errors are detected during operation.
Solution Approach 2:
The patent implements a feedback mechanism where the memory controller continuously monitors ECC check results from dual memory devices, estimates address line errors based on this feedback, and dynamically adjusts memory line enable/disable states and data switching decisions in real-time, creating a closed-loop error management system.
2Reliability
If error checking is performed on all data accesses, then reliability is improved through real-time error detection, but processing speed deteriorates due to additional checking overhead
Solution Approach 1:
The patent applies partial error checking by performing ECC checks selectively based on the estimated probability of address line errors. The memory controller estimates address line error likelihood and only performs comprehensive error checking and data switching when errors are suspected, rather than checking all data accesses uniformly, thus reducing overhead while maintaining reliability.
Solution Approach 2:
The patent performs preliminary estimation of address line errors using ECC check results before initiating full data access operations. By estimating errors in advance based on parity check outcomes, the system can skip unnecessary full error checking procedures for normal operations while maintaining thorough verification when errors are detected, optimizing the balance between speed and reliability.
3Reliability
If dual memory devices with independent address lines are used, then reliability is improved through redundancy, but device complexity increases due to additional memory components and control logic
Solution Approach 1:
The patent merges the error management functions of dual memory devices into a unified control mechanism. The memory controller integrates ECC checking, address line error estimation, and data switching logic into a single coordinated system that manages both memory devices simultaneously, reducing the effective complexity of controlling redundant memory compared to managing separate error handling systems.
Solution Approach 2:
The memory controller performs multiple functions using a single integrated unit: it manages both dual memory devices, performs ECC checking, estimates address line errors, controls memory line enabling/disabling, and manages data switching. This multi-functional approach reduces overall system complexity by consolidating what would otherwise require separate specialized components for each function.
Data Source
AI summary
An estimating unit estimates, when there is a request for data in a system in which an error checking unit of data is formed with a plurality of memories each of which is a dual memory having an independent address line, whether an error has occurred on the address line based on a result of an error checking for data related to the request. A control unit generates, when it is estimated that an error has occurred on the address line, error data of the data related to the request, and controls the memory in such a manner that one line of the dual memory is disabled by switching the data related to the request to generated error data.