Memory Controller Logical to Physical Address Translation Map
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Solution Overview
Problem
Current systems for data storage devices lack efficient direct communication between host devices and flash memory devices, requiring driver intervention and leading to increased CPU processing overhead and latency.
Innovation Solution
A data storage device with a memory controller that receives a logical to physical address translation map from a host, allowing direct communication by translating logical addresses to physical addresses, thereby bypassing the driver and enabling atomic operations for read and write commands.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If driver intervention is used for communication between host and flash memory devices, then communication reliability is improved, but CPU processing overhead increases and latency increases
Solution Approach 1:
The patent extracts the address translation function from the host driver to the memory controller. The memory controller maintains a translation map and performs logical-to-physical address translation independently, removing the need for driver intervention in the communication path and reducing CPU overhead while maintaining reliability through dedicated translation logic.
Solution Approach 2:
The patent introduces a translation map as an intermediary data structure stored in the memory controller. This map enables direct address translation between logical and physical addresses without requiring driver mediation, thereby reducing latency while preserving communication reliability through structured address mapping.
2Reliability
If driver intervention is used for communication between host and flash memory devices, then communication reliability is improved, but CPU processing overhead increases
Solution Approach 1:
The patent extracts the address translation function from the host driver to the memory controller. The memory controller maintains a translation map and performs logical-to-physical address translation independently, removing the need for driver intervention in the communication path and reducing CPU overhead while maintaining reliability through dedicated translation logic.
Solution Approach 2:
The memory controller serves itself by maintaining and using the translation map for address translation. This self-service capability eliminates the need for CPU intervention in address translation operations, reducing processing overhead while ensuring reliable communication through dedicated controller logic.
3Productivity
If direct communication is implemented between host and data storage device, then CPU processing overhead is reduced and latency is reduced, but system complexity increases
Solution Approach 1:
The patent introduces a translation map as an intermediary data structure stored in the memory controller. This map enables direct address translation between logical and physical addresses without requiring driver mediation, thereby reducing latency while preserving communication reliability through structured address mapping.
Data Source
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AI summary
A data storage device includes multiple flash memory devices, where each of the flash memory devices is arranged into multiple blocks having multiple pages for storing data. The data storage device includes a memory controller operationally coupled with the flash memory devices. The memory controller is configured to receive a logical to physical address translation map from a host device, where a physical address includes a physical address for one of the flash memory devices. The memory controller is configured to store the logical to physical address translation map in a memory module on the memory controller, receive read commands directly from an application running on the host device, where the read commands include logical memory addresses that refer to the logical locations on the flash memory devices, and translate the logical addresses to physical memory addresses using the logical to physical address translation map.