Memory Controller Address Mapping for SSD Data Migration

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Solution Overview

Problem

Current memory systems, such as solid state drives (SSDs), face challenges in efficiently managing and migrating data across multiple nonvolatile memory systems connected via networks, particularly in optimizing storage capacity and access latency when handling hot and cold data.

Innovation Solution

A memory system with a controller that manages correspondences between private and public logical addresses across multiple SSDs, allowing for data migration and storage optimization by associating public logical addresses with private addresses on different SSDs based on access frequency, thereby optimizing storage capacity and reducing access latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If data is transferred from one memory system to another via network processing, then data migration is achieved, but access latency increases due to network transfer overhead

Engineering Contradiction:
Improvedata migration capabilityVSAvoidaccess latency
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The system performs preliminary actions by maintaining mapping information that associates public logical addresses with private logical addresses across different memory systems. When data needs to be accessed, the mapping information is already prepared, allowing the host to access data from different SSDs without real-time network processing overhead, thus reducing access latency while enabling data migration capability

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The first memory system acts as an intermediary between the host and the second memory system. The controller of the first memory system maintains mapping information that enables it to intercept and handle access requests for data stored in the second memory system, forwarding these requests appropriately and returning results to the host without requiring the host to directly access the second memory system over the network, thereby reducing access latency

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of operation

If multiple memory systems are managed separately by the host, then address space management is simplified, but storage capacity utilization decreases

Engineering Contradiction:
Improveaddress space managementVSAvoidstorage capacity utilization
Core Design Contradiction:
Ease of operationVSQuantity of substance

Solution Approach 1:

The system merges the management of multiple memory systems by having the first memory system's controller maintain mapping information that spans both the first and second memory systems. This allows the host to access storage capacity from both SSDs through a single interface, effectively combining their storage capacities while maintaining simplified address space management from the host's perspective

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The first memory system is given universal functionality by enabling it to not only store its own data but also to provide access to data stored in the second memory system. The controller maintains mapping information that allows it to handle access requests for both local and remote data, making the first memory system a multi-functional access point for the host

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS11314412B2Memory system including a nonvolatile memory and control method
Publication Date: 2022.04.26 KIOXIA CORP
  • US11314412B2 patent drawing
  • US11314412B2 patent drawing
  • US11314412B2 patent drawing

AI summary

According to one embodiment, a memory system includes a memory system includes a first nonvolatile memory and a controller. The controller controls the first nonvolatile memory. The second memory system includes a second nonvolatile memory. The controller manages information indicative of correspondences between private logical addresses and public logical addresses. The private logical addresses include first private logical addresses and second private logical addresses. Each of the first private logical addresses specifies a location in a first logical address space corresponding to the first nonvolatile memory. Each of the second private logical addresses specifies a location in a second logical address space corresponding to the second nonvolatile memory.