Memory Controller Logical Address Mapping for Rewritable Non-Volatile Memory
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Solution Overview
Problem
The access bandwidth of rewritable non-volatile memory modules is limited due to busy states and differing writing speeds of physical programming units, which restricts data access efficiency in memory storage devices.
Innovation Solution
A memory address management method that maps logical addresses to physical erasing units, programming lower physical programming units first and then upper units within a sequence, allowing for efficient data allocation and expanded access bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data are written into the rewritable non-volatile memory module, then the data storage function is achieved, but the memory module stays busy for a while and cannot accept other write commands, limiting access bandwidth
Solution Approach 1:
The patent segments the physical programming units into lower and upper units within each physical erasing unit, allowing independent programming of these segments. This segmentation enables parallel or overlapping write operations to different segments, reducing the overall busy state duration and expanding access bandwidth.
Solution Approach 2:
The patent implements preliminary action by programming lower physical programming units first, then upper physical programming units within each physical erasing unit. This ordered preliminary programming allows the system to prepare data in lower units while simultaneously performing other operations, reducing idle time and improving access bandwidth.
2Speed
If the writing speed of lower physical programming units is greater than that of upper physical programming units, then faster writing is achieved in lower units, but the differing speeds create bottlenecks in overall write performance
Solution Approach 1:
The patent applies dynamics by adaptively managing the programming sequence based on the different writing speeds of lower and upper physical programming units. The system dynamically adjusts the programming flow to optimize throughput, ensuring that faster lower units are fully utilized while coordinating with slower upper units to maintain balanced overall write performance.
3Productivity
If the number of write commands issued by the host system per second is increased, then higher access bandwidth is achieved, but the memory module becomes overloaded and cannot process commands efficiently
Solution Approach 1:
The patent segments write commands into operations on lower and upper physical programming units separately. This segmentation allows the memory controller to distribute and manage multiple write commands more efficiently across different segments, preventing overload and maintaining reliability even at high command rates.
Data Source
AI summary
A memory address management method, a memory controller, and a memory storage device are provided. The memory address management method includes: obtaining memory information of a rewritable non-volatile memory module and formatting logical addresses according to the memory information to establish a file system, such that an allocation unit of the file system includes a lower logical programming unit and an upper logical programming unit. Here, the memory information includes a programming sequence, the allocation unit starts with the lower logical programming unit and ends with the upper logical programming unit, and an initial logical address of a data region in the file system belongs to the lower logical programming unit. Accordingly, an access bandwidth of the memory storage device is expanded.