Memory Controller Logical Address Redirection for Secure Pre-Boot Updates
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing nonvolatile memory systems face challenges in securely updating and managing pre-boot authentication areas, particularly in ensuring data integrity and reliability during the update process, especially when the update area has discontinuous logical block addresses.
Innovation Solution
A nonvolatile memory system with a memory controller that redirects logical block addresses to specific logical page numbers in the second or third logical areas for writing data, allowing for secure and reliable updates of pre-boot authentication areas, even when the update area has discontinuous logical block addresses, by managing physical storage areas based on multiple logical areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the memory controller uses discontinuous logical block addresses for the update area, then the pre-boot authentication area can be updated, but the data integrity and reliability during the update process deteriorates
Solution Approach 1:
The patent divides the storage area into distinct logical areas: a first logical area for normal data storage and a second logical area for pre-boot authentication area updates. This segmentation allows the controller to manage update operations separately from normal data operations, ensuring that discontinuous logical block addresses in the update area do not compromise overall data integrity. The mapping table is also segmented to track logical block addresses specifically for the second logical area.
Solution Approach 2:
The patent introduces a mapping table as an intermediary structure that translates logical block addresses to physical addresses. This mapping table acts as a mediator between the host's write commands and the actual storage locations, ensuring that even when logical block addresses are discontinuous, the physical storage maintains proper data integrity and sequential writing patterns for the pre-boot authentication area.
2Reliability
If the memory controller manages physical storage area based on multiple logical areas, then the secure update of pre-boot authentication area is improved, but the device complexity increases
Solution Approach 1:
The memory controller is designed with multi-functionality to handle both normal data storage operations and pre-boot authentication area update operations through a unified interface. The controller can switch between managing the first logical area for general storage and the second logical area for secure updates, eliminating the need for separate physical management systems and reducing overall device complexity despite the multiple logical areas.
Solution Approach 2:
The patent implements preliminary actions by pre-configuring the mapping table with the relationship between logical block addresses and physical addresses before update operations begin. The controller pre-establishes the boundaries and management rules for the first and second logical areas, allowing secure updates to proceed without real-time complex decision-making, thereby reducing operational complexity while maintaining security.
3Ease of operation
If the host writes data to the update area with discontinuous logical block addresses, then the update operation can proceed, but the writing speed and efficiency deteriorates
Solution Approach 1:
The mapping table serves as an intermediary that buffers the impact of discontinuous logical block addresses on writing speed. By translating logical addresses to physical addresses in advance and managing the mapping efficiently, the controller minimizes the performance penalty of discontinuous addressing, allowing update operations to proceed smoothly while maintaining reasonable writing speeds through optimized address translation.
Data Source
AI summary
A nonvolatile memory system includes a nonvolatile memory device having a physical storage area, and a memory controller managing the physical storage area on the basis of first and second logical areas. The memory controller is configured to receive a logical block address range corresponding to a part of the first logical area and a command from a host and is configured to receive data, a logical block address and a write command from the host to perform an update with respect to the second logical area. When, in the update operation, the received logical block address is included in the logical block address range, the memory controller, in response to the write command, redirects the received logical block address to a logical page number of the second logical area so that the data is written in the second logical area.