Memory Controller Address Remapping for Defective Cell Bypass
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Solution Overview
Problem
High integration and complexity in semiconductor memory devices lead to decreased yield rates and processing speed due to defective memory cells, which existing technologies fail to effectively address.
Innovation Solution
A memory controller that detects defective cells using a content addressable memory (CAM) and remaps addresses to redirect commands to redundancy areas, maintaining fast data processing speeds by queuing and prioritizing commands and addresses to bypass defective cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If high integration and large capacity are implemented in semiconductor memory devices, then memory capacity and functionality are improved, but yield rate decreases due to increased defective cells
Solution Approach 1:
The memory device is divided into normal memory areas and redundancy memory areas. Defective cells are isolated and replaced by redirecting addresses to redundancy areas, segmenting the impact of defects from the overall memory system.
Solution Approach 2:
A memory controller is introduced as an intermediary between the host and memory device. It detects defective cells and performs address remapping to redirect commands away from defective cells, preventing direct access to faulty memory locations.
2Reliability
If traditional repair methods are used for defective memory cells, then defective cells can be replaced, but processing speed decreases due to additional repair operations
Solution Approach 1:
Defective cell detection and address remapping are performed in advance before normal memory operations. The memory controller pre-identifies defective cells and prepares remapped addresses, so that when a command is issued, the system can immediately use the remapped address without additional repair operations during data processing.
Solution Approach 2:
The memory controller continuously monitors and manages address remapping in the background without interrupting normal memory operations. This allows repair functions to operate continuously alongside data processing, maintaining high processing speed while ensuring defective cells are handled.
3Reliability
If address remapping is performed for defective cells, then defective cells can be bypassed, but command processing time increases due to additional detection and remapping operations
Solution Approach 1:
The memory controller performs defective cell detection and address remapping in advance, before commands are executed. Remapped addresses are prepared and stored, so that during normal operations, the controller can directly use pre-computed remapped addresses without performing detection and remapping at the time of command execution.
Solution Approach 2:
The memory controller autonomously handles address remapping without requiring external intervention or additional processing steps from the host system. The controller self-manages the detection, remapping, and command redirection process, minimizing external overhead and processing time.
Data Source
AI summary
Provided are a memory controller, a memory system including the memory controller, and an operating method performed by the memory controller. The operating method includes operations of queuing a first command in a first queue, detecting a fail of a first address that corresponds to the first command, when the first address is determined as a fail address, queuing a second address and a second command in the first queue, wherein the second address is obtained by remapping the first address and the second command corresponds to the second address, and outputting the second command and the second address from the first queue.