Memory Controller Address Remapping for Read Disturbance Prevention
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Solution Overview
Problem
Next-generation memory devices face reading errors due to reading disturbances in memory cells adjacent to the control circuit, which are not effectively addressed by existing technologies.
Innovation Solution
A memory controller with an address control block that remaps write target addresses and uses an error correction code (ECC) to correct read data, preventing reading disturbances by storing data in adjacent memory cells when the write data has a specific logic level within a correctable range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If data is stored in memory cells adjacent to the control circuit, then memory capacity is increased, but reading errors occur due to reading disturbance
Solution Approach 1:
The system performs preliminary analysis of write data patterns before storing data in adjacent memory cells. The data determination block counts the number of write data with a specific logic level and compares it with a reference value to predict potential reading disturbances, taking preventive action before the actual write operation occurs
Solution Approach 2:
The memory system segments the data storage process by dividing it into normal write operations and remapped write operations. When reading disturbances are predicted, the system segments the affected data and stores it in non-adjacent memory cells separately from normally accessed data
2Reliability
If address remapping is performed to prevent reading disturbance, then reading accuracy is improved, but device complexity increases
Solution Approach 1:
The system applies address remapping selectively only to memory cells adjacent to the control circuit that are susceptible to reading disturbances. The data determination block identifies specific write target addresses that require remapping based on local conditions, rather than remapping all addresses universally
Solution Approach 2:
The address control block acts as an intermediary between the write command and the memory cell array. It receives write commands, determines whether remapping is needed based on data patterns, and selectively remaps addresses only when necessary, mediating between the conflicting requirements of capacity and reliability
3Quantity of substance
If the number of write data with specific logic level is high, then data density is increased, but reading disturbance occurs in adjacent memory cells
Solution Approach 1:
The data determination block performs preliminary counting of write data with a specific logic level before the write operation. By comparing this count with a reference value, the system predicts potential reading disturbances in advance and takes preventive remapping action before the harmful effect can occur
Solution Approach 2:
The system uses feedback from the data pattern analysis to control the address remapping decision. The data determination block continuously monitors write data patterns and provides feedback to the address control block, which adjusts addressing in real-time based on the detected data distribution
Data Source
AI summary
A memory controller may include an address control block. The address control block may be configured to remap a write target address when a number of write data having a first logic level is within a correctable range and when a level of a datum corresponding to the write target address has the first logic level.