Memory Controller Concurrent Command Execution via Address Separation
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Solution Overview
Problem
Current memory controllers for non-volatile memory devices face challenges in optimizing multi-plane operating speed, particularly in determining whether multiple commands can be concurrently executed at different addresses, leading to inefficiencies in data processing and potential data loss during power off states.
Innovation Solution
A memory controller that receives address separation commands from a host to determine if multiple commands can be concurrently executed at different addresses, using a microprocessor to decode and map commands and addresses, allowing for concurrent or non-concurrent execution based on established relationships between them, thereby enhancing multi-plane operating speed and minimizing data loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the memory controller processes commands sequentially without address state separation, then the control logic is simple, but the multi-plane operating speed is limited and data processing efficiency is reduced
Solution Approach 1:
The patent applies segmentation by introducing address state separation commands that divide the address processing into distinct states. The memory controller separates address processing into phases where it can identify and execute commands at different addresses concurrently, thereby increasing multi-plane operating speed while managing complexity through structured state management.
Solution Approach 2:
The patent implements dynamics by enabling the memory controller to adaptively determine whether to execute commands concurrently or sequentially based on the address relationships. The controller dynamically adjusts its operation mode (concurrent or sequential execution) depending on the specific address states and commands received, optimizing performance for each scenario.
2Productivity
If the memory controller executes multiple commands concurrently at different addresses, then the data processing efficiency increases, but the risk of data loss during power off states increases
Solution Approach 1:
The patent applies preliminary action by having the memory controller receive and process address state separation commands in advance before executing the actual data operations. The controller pre-determines the address relationships and execution strategy, allowing it to manage concurrent operations more safely and reduce data loss risk during power off states.
Solution Approach 2:
The patent implements feedback mechanisms where the memory controller continuously monitors the execution status of concurrent commands and address states. This feedback allows the controller to detect and respond to potential data loss conditions, adjusting operations to maintain reliability while preserving the benefits of concurrent processing for improved productivity.
3Speed
If the memory controller uses address state separation commands to determine concurrent execution, then the multi-plane operating speed increases, but the command processing time increases
Solution Approach 1:
The patent applies merging by combining the address state separation function with the existing command processing pipeline. Rather than adding a separate sequential step, the address state separation is integrated into the command decoding and execution determination process, allowing the controller to simultaneously analyze address relationships and prepare for concurrent execution without significant time penalty.
Data Source
AI summary
A memory controller includes a first interface and a microprocessor. The first interface is configured to receive a first command, a first address, an address state separation command, and a second address, the first address corresponding to the first command, and the address state separation command separating the first and second addresses from each other. The microprocessor is configured to decode the first command, map the first address to a non-volatile memory device, execute the first command relative to the first address mapped to the non-volatile memory device, and determine a relation between the first address and the second address. The microprocessor is further configured to selectively execute the second command relative to the second address mapped to the non-volatile memory device concurrently with the first command based on the relation between the first address and the second address.