Nonvolatile Memory Controller Address Translation for Write Speed
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Solution Overview
Problem
The reliability of semiconductor memory devices decreases due to charge leakage and reduced voltage margins, leading to decreased write speed, especially in random write operations, necessitating an improvement in storage device performance.
Innovation Solution
A storage system and operating method that converts random logical addresses into sequential device logical addresses using a sequentializer, allowing for improved write performance by allocating a write buffer and managing data storage across multiple buffers to enhance write speed and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple bits are stored in each memory cell to increase storage capacity, then storage capacity is improved, but write speed decreases due to charge leakage and reduced voltage margins
Solution Approach 1:
The patent segments the write operation into multiple phases: collecting write requests in a buffer, converting random logical addresses to sequential physical addresses, and performing batched sequential writes. This segmentation allows the system to maintain high storage capacity while improving write speed by processing multiple bits in an optimized sequence rather than attempting single-bit writes.
Solution Approach 2:
The patent performs preliminary actions by pre-allocating buffer memory, pre-converting logical addresses to physical addresses using a translation layer, and pre-organizing write requests into sequential batches before actual write operations. This preliminary preparation eliminates bottlenecks during the actual write process, thereby improving write speed without compromising storage capacity.
2Adaptability or versatility
If random write operations are performed to meet diverse data access patterns, then data access flexibility is improved, but write speed decreases due to the nature of random access in nonvolatile memory
Solution Approach 1:
The patent introduces an intermediary translation layer (flash translation layer) that sits between the host interface and the nonvolatile memory device. This intermediary converts random logical addresses from the host into sequential physical addresses for the memory device, maintaining data access flexibility while dramatically improving write speed by eliminating the performance penalty of random writes.
Solution Approach 2:
The patent dynamically adjusts the write operation mode based on the pattern of incoming write requests. When random writes are detected, the system dynamically switches to address translation and batched sequential writing. This dynamic adaptation allows the system to maintain flexibility for diverse access patterns while optimizing write speed through sequential operations when appropriate.
Data Source
AI summary
A storage system includes a processor configured to request a write operation of first data corresponding to a first logical address, and requests a write operation of second data corresponding to a second logical address, a memory module including a nonvolatile memory device configured to store the first data and the second data, and a controller configured to convert the first logical address into a first device logical address, and converts the second logical address into a second device logical address based on the first device logical address and a size of the first data, and a storage device configured to store the first data in the storage device based on the first device logical address, and store the second data in the storage device based on the second device logical address.