Memory Controller Address Translation for High-Capacity Storage
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Solution Overview
Problem
Current storage devices face challenges in efficiently managing address inputs for high-capacity memory devices, where the bit number required to express addresses is not sufficiently secured, leading to limitations in addressing units and cycles, which affects operational performance.
Innovation Solution
The implementation of a memory controller that translates logical block addresses into physical block addresses and generates commands to adjust the addressing unit and cycle periods, allowing for flexible input of addresses, such as changing the period or bit number based on requests, to accommodate high-capacity memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the memory capacity is increased to provide high-capacity storage, then the storage capacity is improved, but the bit number required to express addresses becomes insufficient, leading to addressing limitations
Solution Approach 1:
The address input process is segmented into multiple cycles, with the column address being input in a first cycle and the row address being input in a second cycle. This segmentation allows the system to handle larger address spaces by dividing the addressing process into manageable temporal segments, thereby resolving the limitation imposed by insufficient address bits in high-capacity memory devices.
Solution Approach 2:
The system dynamically adjusts the addressing unit and input period based on the command type and memory capacity requirements. The column decoder can operate in different modes (e.g., 1-byte unit or 512-byte unit) depending on the addressing unit indication signal, allowing the system to adapt its addressing mechanism to match the specific needs of high-capacity memory operations.
2Device complexity
If the addressing unit is fixed to maintain simple control logic, then the control complexity is reduced, but the flexibility to accommodate different memory capacities and operations is limited
Solution Approach 1:
The column decoder is designed with multi-functionality to handle different addressing units (1-byte unit or 512-byte unit) based on the addressing unit indication signal. This universal design allows the same hardware structure to adapt to various memory capacities and operation types without requiring separate dedicated circuits for each addressing mode, thereby maintaining control logic simplicity while enhancing addressing flexibility.
Solution Approach 2:
The system changes the addressing unit parameter dynamically based on the command type and memory capacity requirements. By adjusting the addressing unit indication signal, the system can switch between different addressing modes (1-byte or 512-byte units), allowing flexible accommodation of various memory capacities and operations without fundamentally changing the control logic structure.
3Reliability
If the address input period is extended to provide sufficient addressing time, then the addressing completeness is improved, but the operational speed is reduced
Solution Approach 1:
The address input is structured as a periodic action with specific timing cycles. The column address is input during a first cycle, and the row address is input during a second cycle. This periodic structure ensures that addresses are input in sufficient time for high-capacity memory devices while maintaining efficient operational speed through predictable, rhythmic timing patterns that optimize both completeness and speed.
Solution Approach 2:
The column address is input in advance during the first cycle before the row address is input in the second cycle. This preliminary action allows the column decoder to prepare for the subsequent row address input, ensuring that the complete address is ready in time for the memory operation while maintaining efficient timing that prevents speed degradation.
Data Source
AI summary
A memory controller controls an address such that a number of chips included in a memory device can increase. The memory controller includes a flash translation layer configured to translate a logical block address received from a host into a physical block address, wherein the flash translation layer determines an addressing unit of at least one of a plurality of addresses in the physical block address based on a request received from the host and a command controller configured to generate a command representing the addressing unit based on the request.