Memory Controller Address Verification via Stored Location Indicia

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Memory devices face errors due to corrupted address information on the command/address bus, leading to operations being performed at unintended physical addresses, necessitating a method to verify that memory operations are executed at the intended address.

Innovation Solution

A memory device with a controller that stores data and a location indicia corresponding to the address, allowing verification of the address upon data retrieval, and indicating errors if the location indicia does not match the intended address, using techniques such as hashing or checksums to generate and compare location indicia.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If address verification mechanisms are implemented, then reliability of memory operations is improved, but device complexity increases due to additional storage and comparison operations

Engineering Contradiction:
Improvememory operation accuracyVSAvoidcontroller complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by pre-storing location indicia (such as row addresses, bank addresses, or hashed values) alongside the data in the memory array during the write operation. When a read operation occurs, the controller retrieves both the data and the stored location indicia, then verifies them against the current address parameters before proceeding with data output. This pre-storation of verification data eliminates the need for complex real-time address validation logic, thereby improving reliability while managing device complexity.

Inventive Principle:
Principle #10Preliminary action

2Measurement precision

If location indicia are stored with each data word, then measurement precision of address verification is improved, but quantity of stored information increases

Engineering Contradiction:
Improveaddress verification accuracyVSAvoidstorage capacity
Core Design Contradiction:
Measurement precisionVSQuantity of substance

Solution Approach 1:

The patent applies local quality by making the location indicia optional rather than universal. The verification mechanism can be selectively enabled for specific memory regions, data types, or operation modes where address corruption is most likely to occur or where data integrity is most critical. This selective application allows high measurement precision where needed while minimizing the quantity of stored information in regions where verification is less critical, thus resolving the contradiction between verification accuracy and storage overhead.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS10761997B2Methods of memory address verification and memory devices employing the same
Publication Date: 2020.09.01 MICRON TECHNOLOGY INC
  • US10761997B2 patent drawing
  • US10761997B2 patent drawing
  • US10761997B2 patent drawing

AI summary

A memory device and methods for operating the same are provided. The memory device includes an array of memory cells, and a controller configured to receive a data word to be stored at an address in the array and to store, at the address in the array, the data word and a location indicia corresponding to the address. The controller can be further configured to command the array to read the data word from the address, to receive response data from the array, and to verify that a location indicia of the response data corresponds to the address. If the location indicia of the response data does not correspond to the address, the controller can be further configured to indicate an error.