Memory Controller Address Verification via Non-Volatile Location Indicia
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Solution Overview
Problem
Memory devices often experience errors in address information during command/address bus operations, leading to memory operations being performed at unintended physical addresses, necessitating a method to verify the accuracy of memory operations.
Innovation Solution
Incorporating a controller in memory devices that receives read or write commands, decodes addresses, retrieves location indicia from non-volatile memory, and verifies that the operation is performed at the intended address, with the option to store location indicia as a hash, checksum, or subset to balance storage and error tolerance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If address verification is implemented using non-volatile memory to store location indicia, then reliability of memory operations is improved, but device complexity increases
Solution Approach 1:
The patent introduces non-volatile memory as an intermediary component to store location indicia (hash values, checksums, or subsets of addresses). This mediator verifies address accuracy by comparing stored indicia with current address information, resolving the contradiction by adding a dedicated verification layer that improves reliability without requiring the main memory array to perform complex verification functions.
Solution Approach 2:
The patent creates a copy of address information in the form of location indicia (hash values, checksums, or address subsets) stored in non-volatile memory. This copy serves as a verification reference, allowing the system to detect address errors without requiring complex real-time verification mechanisms, thus improving reliability while managing device complexity.
2Reliability
If location indicia are stored as hash or checksum values, then error detection capability is improved, but storage space requirements increase
Solution Approach 1:
The patent applies partial action by storing only portions of address information (location indicia such as hash values, checksums, or address subsets) rather than complete address data. This partial storage approach provides sufficient error detection capability while minimizing storage space requirements, resolving the contradiction between reliability improvement and storage space consumption.
Solution Approach 2:
The patent transforms address information into different parameter representations (hash values, checksums, or subsets) that can be stored efficiently. By changing the parameter form of address data, the system achieves adequate error detection with reduced storage requirements, balancing reliability and storage space considerations.
3Measurement precision
If address verification is performed for all memory operations, then measurement precision of address accuracy is improved, but productivity decreases
Solution Approach 1:
The patent performs preliminary action by pre-storing location indicia in non-volatile memory during device initialization or previous operations. This pre-prepared verification data allows rapid address verification without requiring complex real-time computations, thus improving measurement precision of address accuracy while minimizing impact on productivity during actual memory operations.
Solution Approach 2:
The patent substitutes complex mechanical verification processes with simpler comparison operations. Instead of performing comprehensive address validation through complex circuitry, the system uses straightforward comparisons between stored location indicia and current address information, achieving high measurement precision with minimal overhead to memory operation speed.
Data Source
AI summary
A memory device and methods for operating the same are provided. The memory device includes an array of memory cells, a non-volatile memory, and a controller. The controller is configured to receive a read command to read a data word from an address of the array and decode the address to generate a decoded address. The controller is further configured to retrieve response data from the decoded address of the array, retrieve a location indicia corresponding to the decoded address from the non-volatile memory, and verify that the location indicia corresponds to the address. The controller can optionally be further configured to indicate an error if the location indicia does not correspond to the address.