Memory Controller Address Virtualization for Predictable Storage Latency
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Solution Overview
Problem
Existing non-volatile memory systems face challenges in managing complex hardware-specific media management tasks, leading to performance degradation and resource conflicts, while existing virtualization techniques result in unpredictable latency and reduced capacity due to overprovisioning.
Innovation Solution
A memory controller that subdivides memory addresses into hierarchical fields, allowing virtualization of physical structures and masking defects, enabling configurable block devices with optimized performance characteristics and seamless integration with next-generation technologies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If existing virtualization techniques are used to manage memory addresses, then host system design is simplified, but latency becomes unpredictable and capacity is reduced due to overprovisioning
Solution Approach 1:
The patent segments the memory address space into distinct hierarchical fields (channel, die, plane, block, page) that can be independently configured and mapped. This segmentation allows the host system to see a simplified virtualized address space while the controller independently manages each field, achieving both ease of operation and predictable latency by eliminating unnecessary mapping overhead.
Solution Approach 2:
The memory controller acts as an intermediary between the host system and the physical memory structures. It translates simplified host addresses into physical memory locations using a direct hierarchical mapping approach, providing the mediating function that simplifies host design while maintaining predictable performance through efficient address translation without overprovisioning.
2Ease of operation
If existing virtualization techniques are used to manage memory addresses, then host system design is simplified, but storage capacity is reduced due to overprovisioning
Solution Approach 1:
By segmenting the address space into hierarchical fields that directly map to physical memory structures, the patent eliminates the need for overprovisioning buffers. Each segment (channel, die, plane, block, page) can be independently configured to match actual physical capacity, allowing full utilization of storage resources while maintaining simplified host interfacing.
Solution Approach 2:
The patent enables dynamic configuration of address field parameters (width, mapping relationships) to optimize capacity utilization. The hierarchical address fields can be configured to match the actual physical memory topology, allowing the system to adapt parameters to maximize storage capacity while maintaining the simplified virtualized interface for the host.
3Productivity
If complex hardware-specific media management tasks are managed directly, then performance is maintained, but resource conflicts occur and performance degradation happens
Solution Approach 1:
The patent extracts complex media management functions from the host system and embeds them directly in the memory controller. The controller independently manages channel, die, plane, block, and page operations, removing the burden of complex hardware-specific management from the host while maintaining high performance through dedicated controller intelligence.
Solution Approach 2:
The memory controller performs self-service by autonomously managing its own address translation, resource allocation, and media management tasks. The hierarchical address fields enable the controller to independently coordinate channels, dies, planes, blocks, and pages without external intervention, eliminating resource conflicts and performance degradation while maintaining high productivity.
4Ease of manufacture
If fixed memory architecture is used, then manufacturing is simplified, but adaptability to next-generation technologies is reduced
Solution Approach 1:
The patent implements a dynamic address translation architecture where the hierarchical field configurations can be adjusted to match different physical memory topologies. The controller can adapt the channel-die-plane-block-page mapping relationships to accommodate evolving memory technologies while maintaining the same simplified host interface, enabling forward compatibility without sacrificing manufacturing simplicity.
Solution Approach 2:
The hierarchical address field structure provides a universal interface that can work with various memory technologies and configurations. The same five-field architecture (channel, die, plane, block, page) can be configured to support different physical arrangements and future memory technologies, making the system universally compatible while maintaining ease of manufacture through standardized controller design.
Data Source
AI summary
This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.