Memory Controller Adjacent Cell Testing for Error Detection
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Solution Overview
Problem
Current computing systems fail to effectively detect and prevent uncorrectable errors in memory cells adjacent to those experiencing errors during workload operations, leading to potential data loss and system instability.
Innovation Solution
A computing system and method that includes a memory device and a memory controller capable of performing Built-In Self-Test (BIST) or scrub engine operations on adjacent memory cells to detect and generate error information, allowing the host to control access based on this information, thereby preventing access to error-prone memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the computing system performs test operations on adjacent memory cells using BIST engine or scrub engine, then error detection capability is improved, but device complexity and processing time increase
Solution Approach 1:
The system performs test operations on adjacent memory cells proactively before errors occur, using BIST engine for self-testing and scrub engine for periodic scanning. This preliminary detection prevents errors from propagating, resolving the contradiction by establishing reliability through advance testing without requiring complex external test equipment.
Solution Approach 2:
The memory controller implements self-diagnostic capabilities through integrated BIST and scrub engines that automatically test adjacent memory cells without external intervention. This self-service approach improves error detection while avoiding the complexity of external testing infrastructure, as the system monitors and tests itself autonomously.
2Reliability
If the host controls access to memory cells based on error information, then data integrity is improved, but processing speed decreases due to access blocking
Solution Approach 1:
The host selectively controls access based on localized error information from specific adjacent memory cells, rather than blocking entire memory regions. This targeted approach maintains data integrity for affected cells while preserving processing speed for unaffected cells, resolving the contradiction through spatially differentiated access control.
Solution Approach 2:
The memory address space is segmented into affected and unaffected regions based on error detection results. The host applies access control policies selectively to specific memory segments rather than uniformly across all memory, allowing parallel processing in safe regions while isolating only the problematic cells that require protection.
3Measurement precision
If test operations are performed on all adjacent memory cells, then measurement precision is improved, but loss of time increases due to extensive testing
Solution Approach 1:
The system performs test operations on a partial set of adjacent memory cells rather than exhaustive testing of all possible cells. The BIST engine tests cells immediately adjacent to detected errors, while the scrub engine performs periodic scanning of broader regions. This partial testing approach achieves sufficient measurement precision for error containment while minimizing time loss through strategic selection of test targets.
Data Source
AI summary
A computing system includes: a memory device including a memory cells; a memory controller configured to control the memory device; and a host configured to detect an occurrence of an error in a first memory cell of the memory device while performing an operation corresponding to a workload and transmit, to the memory controller, a target address corresponding to the first memory cell and a request for a test operation on adjacent memory cells that are adjacent to the first memory cell. The memory controller controls the memory device to perform the test operation on the adjacent memory cells by using at least one of a Built-In Self-Test (BIST) engine or a scrub engine based on the target address and generate memory error information including information associated with a second memory cell in which the error occurs, the second memory cell being one of the adjacent memory cells. The host controls an access to the second memory cell based on the memory error information.