Memory Controller Adjacent Refresh Commands
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Solution Overview
Problem
Modern DRAM chips experience data corruption due to frequent activations of rows, which can upset adjacent memory cells, leading to loss of original data, and existing solutions like Targeted Row Refresh (TRR) require significant time and system overhead.
Innovation Solution
The introduction of new adjacent commands, such as Activate Adjacent (ACTADJ) and Precharge Adjacent (PREADJ), which allow for the immediate refresh of adjacent rows before accessing a subject row, reducing data corruption and system overhead compared to TRR.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Targeted Row Refresh (TRR) mode is used to prevent data corruption, then data reliability is improved, but system overhead and access time increase significantly
Solution Approach 1:
The patent applies preliminary action by proactively refreshing adjacent rows before they can be corrupted by excessive activations. The memory controller monitors activation counts and issues refresh commands to adjacent rows in advance, preventing data corruption before it occurs rather than reacting after corruption happens.
Solution Approach 2:
The patent introduces an intermediary mechanism - a counter and monitoring system that tracks row activations and mediates between normal memory operations and refresh operations. This intermediary layer decides when adjacent rows need refreshing based on activation counts, enabling timely refresh without requiring full TRR mode overhead.
2Reliability
If TRR mode is entered to protect adjacent rows, then data corruption is prevented, but memory access speed decreases due to mode switching overhead
Solution Approach 1:
The patent applies partial action by refreshing only the specific adjacent rows that need protection based on activation patterns, rather than entering full TRR mode which requires all banks to be idle. This selective approach refreshes only the necessary rows (exactly what's needed, no more), maintaining speed while ensuring data integrity.
3Productivity
If frequent row activations are performed to meet memory access demands, then system productivity is improved, but adjacent rows become corrupted
Solution Approach 1:
The patent implements feedback by continuously monitoring row activation counts and using this information to trigger refresh operations on adjacent rows. The counter tracks how many times a row has been activated, and when a threshold is reached, the system responds by refreshing adjacent rows, creating a closed-loop control system that balances productivity and reliability.
Data Source
AI summary
In one form, a memory includes a memory bank, a page buffer, and an access circuit. The memory bank has a plurality of rows and a plurality of columns with volatile memory cells at intersections of the plurality of row and the plurality of columns. The page buffer is coupled to the plurality of columns and stores contents of a selected one of the plurality of rows. The access circuit is responsive to an adjacent command and a row address to perform a predetermined operation on the row address, and to refresh first and second addresses adjacent to the row address. In another form, a memory controller is adapted to interface with such a memory to select either a normal command or an adjacent command based on a number of activate commands sent to the row in a predetermined time window.