Memory Controller Dynamic Address Allocation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current memory systems face challenges in optimizing access performance, particularly in managing write operations across multiple memory blocks and dies, leading to inefficiencies in both read and write operations due to suboptimal physical address allocation schemes.
Innovation Solution
A memory system with a controller that determines the physical address allocation scheme based on the attribute of a write command, either sequentially selecting memory blocks in ascending order of dies or interleaving data across dies to optimize access performance, thereby improving both sequential read and write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a fixed physical address allocation scheme is used, then the address management is simple, but the access performance cannot be optimized for different write operation patterns
Solution Approach 1:
The patent implements dynamic address allocation by switching between different allocation schemes (first scheme and second scheme) based on the type of write operation. The controller determines which scheme to use according to operation characteristics, making the address management system adaptive rather than static, thereby resolving the contradiction between simplicity and performance optimization.
Solution Approach 2:
The patent changes the parameter of address allocation strategy based on write operation attributes. By selecting different allocation schemes (sequential vs. interleaved) depending on the operation type, the system optimizes access performance for different scenarios without requiring a completely different management approach, balancing adaptability and complexity.
2Productivity
If sequential memory block selection is used, then the address allocation is simple, but the parallel processing capability is reduced
Solution Approach 1:
The patent segments the memory block selection process into two distinct approaches: sequential selection for certain operations and interleaved selection for others. By dividing the address allocation into different schemes based on operation type, the system can exploit parallel processing capabilities when needed while maintaining simplicity for other cases, thus improving productivity without excessive complexity.
Solution Approach 2:
The patent dynamically selects between sequential and interleaved block selection methods based on the write operation characteristics. This dynamic approach enables the system to maximize parallel processing capability for suitable operations while avoiding unnecessary complexity for operations that don't benefit from interleaving, resolving the contradiction between productivity and complexity.
3Speed
If interleaved data distribution across dies is used, then the access performance is improved, but the control overhead increases
Solution Approach 1:
The patent implements conditional interleaved data distribution by selecting this approach only for specific write operation types. The controller dynamically determines whether to apply interleaved distribution based on operation attributes, achieving high access speed for suitable cases while minimizing control overhead by not applying the complex scheme universally.
Solution Approach 2:
The patent changes the data distribution parameter from always-sequential to conditionally-interleaved based on write operation characteristics. This selective application of interleaved distribution optimizes access speed for operations that benefit from it while avoiding the control overhead for operations that don't require such optimization, resolving the contradiction between speed and control complexity.
Data Source
AI summary
An operation method of a memory system includes a memory device including plural level memory cells. The operation method includes allocating a physical address according to a physical address allocation scheme which is determined based on an attribute of a write command; and performing a write operation on the allocated physical address.