Memory Controller Alternating Buffers for Multi-Core Access Contention
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Solution Overview
Problem
Integrated circuits face challenges in reducing dynamic latency and memory access contention among multiple processing cores accessing shared memory banks, with existing solutions increasing circuit complexity and area.
Innovation Solution
A memory controller design that includes alternating buffers and masks for each core to manage access requests, allowing dynamic determination of access sequences without significantly increasing complexity, and uses a pipelining step to optimize bandwidth utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If address interleaving is used to reduce dynamic latency, then memory access speed is improved, but memory access conflict increases when multiple cores access the same memory bank
Solution Approach 1:
The memory system is divided into multiple memory banks, and the address space is segmented through interleaving to distribute access requests across different banks. This segmentation reduces contention by allowing simultaneous access to different segments (banks) while maintaining high access speed.
Solution Approach 2:
The patent implements dynamic arbitration that adapts to real-time memory access patterns. The arbitration mechanism dynamically adjusts priority levels and access sequences based on current contention conditions, transforming the static memory access structure into a dynamic system that optimizes both speed and conflict resolution.
2Adaptability or versatility
If an arbiter with select logic is included to dynamically determine access sequence, then access fairness is improved, but circuit complexity and area increase
Solution Approach 1:
The arbiter is designed with multi-functionality to handle various arbitration schemes (round-robin, priority-based, dynamic) within a single unified structure. This universal design provides configurable access sequences and fairness mechanisms without requiring separate dedicated circuits for each arbitration mode, thereby controlling complexity.
Solution Approach 2:
The arbitration behavior is controlled by changing parameters such as priority levels and selection signals rather than reconfiguring the entire circuit structure. This parameter-based control allows dynamic determination of access sequences while maintaining a fixed, manageable circuit architecture.
3Speed
If priority-based arbitration is used to resolve memory access conflicts, then access order is improved, but starvation of low-priority cores occurs
Solution Approach 1:
The patent incorporates periodic priority inversion or rotation mechanisms that systematically give access to low-priority cores at regular intervals. This periodic action ensures that while high-priority cores receive timely service maintaining throughput, low-priority cores are periodically served to prevent starvation and ensure access fairness.
Solution Approach 2:
The arbitration system uses feedback mechanisms to monitor the access patterns and priority levels of different cores. When low-priority cores are detected to be starved, the feedback triggers priority adjustments or preemptions to restore fairness, thereby maintaining both throughput and reliability through closed-loop control.
Data Source
AI summary
A memory controller includes a large combinational cloud to serve multi-core-to-multi-bank memory accesses which causes congestion and routing delays at physical design level especially in lower technology nodes thus limiting the frequency of operation. Present invention proposes an architecture to process sequences of access requests from multiple processing cores using alternating processing to generate sequences of granted access requests to one or more memory banks. For each processing core, first and second buffers store access requests. When an access request from one buffer is granted, that buffer is configured to receive a new access request and processing is performed to determine whether to grant an access request stored in the other buffer. The invention can maintain optimal bandwidth while providing desired sequences of the granted access requests and solving physical congestion issues.