Memory Controller Arbitration for Internal Processor Access
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Solution Overview
Problem
In memory systems with internal and external processors, simultaneous access to a shared memory array can lead to conflicts and increased power consumption due to the need for external buses for data transfer, which is particularly disadvantageous in mobile devices.
Innovation Solution
Implementing a memory device with an internal processor, such as a compute engine with ALUs, embedded on the same chip as the memory array, and using a control interface to arbitrate access between external and internal processors, eliminating the need for external buses and reducing power consumption by enabling direct communication for request and grant signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If an external bus is used to transfer data between memory array and processor, then data transfer is enabled, but power consumption increases
Solution Approach 1:
The patent combines the processor and memory array into a single integrated device, allowing direct communication between the processor and memory array without requiring external buses. This merging eliminates the power consumption associated with external data transfer while maintaining full functionality.
2Productivity
If multiple processors access the memory array simultaneously, then processing capability is improved, but data collisions increase
Solution Approach 1:
The patent segments the memory array into multiple banks, allowing different processors to access different banks simultaneously. This segmentation enables parallel processing while eliminating data collisions by providing dedicated access paths for each processor to its assigned memory bank.
Solution Approach 2:
The patent introduces a controller as an intermediary between multiple processors and the memory array. The controller manages and coordinates access requests from multiple processors, arbitrating between them to prevent data collisions while maintaining efficient parallel processing operations.
Data Source
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AI summary
Systems, methods of operating a memory device, and methods of arbitrating access to a memory array in a memory device having an internal processor are provided. In one or more embodiments, conflicts in accessing the memory array are reduced by interfacing an external processor, such as a memory controller, with the internal processor, which could be an embedded ALU, through a control interface. The external processor can control access to the memory array, and the internal processor can send signals to the external processor to request access to the memory array. The signals may also request a particular bank in the memory array. In different embodiments, the external processor and the internal processor communicate via the control interface or a standard memory interface to grant access to the memory array, or to a particular bank in the memory array, for example.