Memory Controller Arbitration Periods for NAND Flash Cycle Delays
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Solution Overview
Problem
In non-volatile semiconductor memory systems, such as NAND flash memory, variations in memory chip quality lead to differences in non-volatilization processing times, causing performance degradation when a uniform arbitration period is set for all chips, resulting in cycle delays and reduced overall system performance.
Innovation Solution
A memory system with a memory controller that sets a unique arbitration period for each memory chip based on its individual non-volatilization execution time, ensuring that chips with longer processing times do not hinder those with shorter times, thereby minimizing cycle delays and maintaining system performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a uniform arbitration period is set for all memory chips, then the system structure is simple and easy to manage, but chips with longer processing times cause cycle delays that reduce overall system performance
Solution Approach 1:
The patent applies local quality by setting different arbitration period values for different memory chips based on their individual non-volatilization processing characteristics. Each chip is assigned a customized arbitration period that matches its specific processing speed, allowing faster chips to complete operations without waiting for slower chips, thereby eliminating cycle delays while maintaining manageable system complexity through automated characterization.
2Reliability
If the arbitration period is extended to accommodate slower chips, then all chips can complete processing without cycle delays, but faster chips experience unnecessary waiting time reducing overall throughput
Solution Approach 1:
The patent implements parameter changes by dynamically adjusting the arbitration period value for each memory chip based on its measured non-volatilization processing time. During an initialization phase, each chip's processing time is characterized and used to set its specific arbitration period parameter. This ensures that the arbitration period is optimized for each chip's speed characteristics, allowing reliable processing completion without unnecessary waiting time for faster chips.
3Productivity
If individual arbitration periods are set for each memory chip, then processing efficiency is maximized by eliminating cycle delays, but the system complexity increases due to multiple arbitration period settings
Solution Approach 1:
The patent applies preliminary action by performing non-volatilization processing time measurement and arbitration period setting during an initialization phase before normal operation begins. This preliminary characterization of each chip's processing characteristics allows the system to establish optimized arbitration periods in advance, eliminating the need for complex real-time adjustments during operation while maximizing processing efficiency from the start.
Data Source
AI summary
A memory system includes a plurality of non-volatile memory chips divided into a plurality of storage areas, and a memory controller that is connected to the plurality of memory chips to control an operation of each memory chip. The memory controller is configured to set an arbitration period separately for each of the respective storage areas, and to execute a process to store data into the storage areas one after another in accordance with the arbitration period set therefor.