Memory Controller Arbitration Logic for Shared Data Bus Efficiency
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Solution Overview
Problem
Existing memory controllers experience a decrease in memory utilization efficiency due to the need to wait for a period before issuing commands to different memories after a read/write command, leading to inefficient memory switching when a memory access request is stopped to a memory to which the preceding read/write command was issued.
Innovation Solution
A memory controller with a holding circuit to store access requests and a control circuit that selects arbitrary access requests, preventing selection of access requests to memories other than the one that received the preceding read/write command for a predetermined period after the command issuance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the memory controller switches memories to satisfy timing constraints and avoid signal collision, then shared signals do not collide, but a gap occurs in the data bus causing decreased memory utilization efficiency
Solution Approach 1:
The memory controller predicts future memory access patterns and pre-positions memory banks to minimize switching gaps. By anticipating upcoming access requests, the controller prepares the memory system in advance, reducing the impact of timing constraints on overall utilization efficiency.
2Device complexity
If the memory controller arbitrates memory access requests to reduce memory switching times, then the number of switching operations decreases, but memory utilization efficiency still deteriorates when access requests are stopped to the preceding memory
Solution Approach 1:
The memory controller dynamically adjusts arbitration decisions based on real-time memory access patterns and timing constraints. When a memory access request is stopped to the preceding memory, the controller modifies its arbitration behavior to maintain optimal utilization, transitioning from static arbitration to adaptive dynamic control.
Solution Approach 2:
The controller monitors memory access outcomes and uses this feedback to adjust future arbitration decisions. By detecting when access requests are stopped to the preceding memory, the controller learns from past performance and optimizes subsequent arbitration to prevent utilization deterioration.
3Reliability
If the memory controller waits for the read/write command period to elapse before issuing commands to different memories, then timing constraints are satisfied, but memory access latency increases during the waiting period
Solution Approach 1:
The memory controller maintains continuous useful action by overlapping command issuance to different memories with the read/write command execution period. Through pipelining and parallel operations, the controller ensures that waiting periods are minimized and memory resources remain actively utilized throughout the timing constraint window.
Data Source
AI summary
A memory controller that issues a command to access a plurality of memories sharing a data signal, the memory controller comprising: a holding circuit configured to hold a read and/or write access request; and a control circuit configured to select an arbitrary access request from the access requests held in the holding circuit and to issue a read command and/or a write command, wherein the control circuit controls not to select, for a predetermined period from issuance of a read command and/or a write command immediately preceding, an access request to a memory other than a memory to which the read command and/or the write command was issued immediately preceding, from among the access requests held in the holding circuit.