Memory Controller Asymmetric Data Storage
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Solution Overview
Problem
Current memory devices face challenges in maintaining data integrity due to differing retention times of memory cell phases, leading to faster deterioration of data stored in cells with lower retention times, resulting in defective data over time.
Innovation Solution
A memory device with a controller that selects between a first and second situation mode based on the retention times of bit types, disabling or enabling a flag to write data into memory macros with longer retention times, and performing error correction codes to optimize data storage and retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If data is stored in memory cells with lower retention time phase, then write operation is simpler, but data correctness deteriorates faster over time
Solution Approach 1:
The system dynamically changes the storage parameter (phase selection) based on retention time characteristics. The controller selects between first and second phases for storing data bits depending on which phase offers longer retention time for that particular bit position, thereby optimizing both write simplicity and long-term data correctness.
Solution Approach 2:
The patent implements a dynamic write operation where the controller adaptively chooses the storage phase for each bit based on real-time retention time assessment. This dynamic selection process allows the system to optimize for data correctness while maintaining write operation efficiency through automated phase selection.
2Reliability
If data is stored in memory cells with higher retention time phase, then data correctness is maintained longer, but write operation becomes more complex
Solution Approach 1:
The controller automatically performs the complex phase selection process without requiring external intervention or complex write operations. The system serves itself by internally managing the phase selection based on retention time characteristics, thereby maintaining data correctness while keeping the write interface simple for the user.
Solution Approach 2:
The controller acts as an intermediary between the data write operation and the memory cells. It translates simple write commands into complex phase-specific operations by selecting the appropriate phase for each bit based on retention time, thereby shielding the user from complexity while ensuring data correctness.
3Reliability
If flag is enabled for asymmetric data store, then data correctness is optimized, but device complexity increases
Solution Approach 1:
The patent implements asymmetric data storage by treating first and second phases differently based on their retention time characteristics. The flag indicates which phase has longer retention time, and the controller applies asymmetric write strategies accordingly, optimizing data correctness while managing complexity through structured asymmetric handling.
Solution Approach 2:
The system changes operational parameters (phase selection, flag state) based on retention time characteristics. By dynamically adjusting these parameters, the controller optimizes data correctness while managing its own complexity through automated parameter management rather than hardwired complex logic.
Data Source
AI summary
A memory device includes a memory array with at least one memory macro, a flag, and a controller. The controller is coupled to the memory array. Each bit of data stored in the at least one memory macro is presented as a first bit type or a second bit type. The controller is configured to select one of a first situation mode and a second situation mode as a selected situation mode according to a first retention time of the first bit type and a second retention time of the second bit type. The first situation mode is that a number of bits with the first bit type in data is larger than a number of bit with the second bit type in data, and the second situation mode is that the number of bit with the first bit type in data is not larger than the number of bits with the second bit type in data. In a write operation of the at least one memory macro, the controller determines that an input data is meet the selected situation mode or not. In response to the input data is meet the selected situation mode, the controller disables the flag and writes the input data into the at least one memory macro. In response to the input data is not meet the selected situation mode, the controller enables the flag, inverts the input data, and writes an inverted input data into the at least one memory macro.