Memory Controller Parallel Authentication Code Generation

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Solution Overview

Problem

Current storage devices lack efficient security read performance, particularly in generating device authentication codes in parallel with data transmission, which can lead to increased read times and vulnerabilities such as replay attacks.

Innovation Solution

A storage device with a write protection area and a memory controller that performs read operations and generates device authentication codes in parallel, using a Message Authentication Code (MAC) algorithm based on shared keys to verify data integrity and prevent unauthorized access.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If device authentication code generation is performed sequentially after data transmission, then security verification is ensured, but total read time increases

Engineering Contradiction:
Improvesecurity verificationVSAvoidtotal read time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The memory controller generates the device authentication code in advance during the data read operation, before the host completes its authentication process. This preliminary generation of authentication code during data transmission eliminates the need for separate sequential authentication operations, thereby reducing total read time while maintaining security verification reliability

Inventive Principle:
Principle #10Preliminary action

2Productivity

If data transmission and authentication code generation are performed sequentially, then processing simplicity is maintained, but security read performance decreases

Engineering Contradiction:
Improvesecurity read performanceVSAvoidparallel processing capability
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent merges the data read operation and device authentication code generation into a single parallel processing workflow. The memory controller simultaneously performs data retrieval from memory and authentication code generation using the read data, combining two previously sequential operations into one unified process that improves security read performance without requiring separate processing stages

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If traditional read operations are used without parallel authentication, then device complexity remains low, but vulnerability to replay attacks increases

Engineering Contradiction:
Improveprotection against replay attacksVSAvoidauthentication mechanism
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The authentication code is generated in advance during the data read operation itself, creating a time-synchronized authentication mechanism. This preliminary generation ensures that the authentication code is always current and tied to the specific data transmission event, preventing replay attacks where intercepted authentication codes might be reused, while adding minimal complexity to the device architecture

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11455102B2Computing system and operating method thereof
Publication Date: 2022.09.27 SK HYNIX INC
  • US11455102B2 patent drawing
  • US11455102B2 patent drawing
  • US11455102B2 patent drawing

AI summary

An electronic device is provided. A storage device includes a memory device and a memory controller. The memory device includes a write protection area. The memory controller controls the memory device to perform a read operation on the write protection area, in response to a series of requests regarding security read that are received from a host, provides read data received from the memory device to the host, and generates a device authentication code based on the read data. The memory controller performs generation of the device authentication code in parallel with provision of the read data to the host.