Autonomous Memory Controller Frequency Scaling Adaptation
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Solution Overview
Problem
Dynamic frequency and voltage scaling (DFVS) in memory controllers is conservative due to high costs of misprediction, leading to less power efficiency and disruption in memory access, as existing systems require processor intervention for updating timing parameters, causing latency and potential system disruptions.
Innovation Solution
A memory controller that autonomously adapts to changes in system clock frequency by storing non-scalable timing characteristics independently of the clock frequency, allowing it to generate new control signals synchronized with the changed frequency without processor intervention, reducing adaptation time and minimizing system disruptions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Extent of automation
If the memory controller waits for processor intervention to update timing parameters when frequency scaling occurs, then the processor can control the adaptation process, but the adaptation time increases and system disruptions occur
Solution Approach 1:
The memory controller autonomously detects frequency changes and updates its timing parameters without requiring processor intervention. The controller monitors the system clock frequency, compares it against stored reference values, and automatically adjusts its internal timing parameters when frequency scaling is detected, eliminating the need for processor-initiated reconfiguration.
Solution Approach 2:
The memory controller pre-loads multiple sets of timing parameters corresponding to different frequency levels into its internal memory. When frequency scaling occurs, the controller quickly selects and applies the appropriate pre-configured timing parameters rather than calculating and programming them in real-time, significantly reducing adaptation latency.
2Reliability
If conservative DFVS algorithms are used to avoid misprediction costs, then system stability is maintained, but power efficiency decreases due to fewer power savings opportunities
Solution Approach 1:
The memory controller continuously monitors the actual system clock frequency and compares it against the frequency at which timing parameters were programmed. When a frequency mismatch is detected, the controller automatically triggers a reconfiguration sequence to update timing parameters, ensuring optimal performance at the current frequency level and enabling more aggressive DFVS algorithms.
3Use of energy by moving object
If timing parameters are updated frequently during frequency scaling, then power efficiency improves, but system disruptions and memory unavailability increase
Solution Approach 1:
The memory controller pre-loads multiple sets of timing parameters corresponding to different frequency levels into its internal memory. When frequency scaling occurs, the controller quickly selects and applies the appropriate pre-configured timing parameters rather than calculating and programming them in real-time, significantly reducing adaptation latency.
Solution Approach 2:
The memory controller implements dynamic timing parameter adjustment by continuously monitoring system clock frequency and automatically switching between different timing parameter sets based on the current frequency level. This dynamic adaptation allows the system to respond quickly to frequency changes without requiring processor intervention or causing memory unavailability.
Data Source
AI summary
A memory controller (40) is adaptable to scaling of a system clock frequency, to enable another device (10) to access a memory (20), and has a part for outputting control signals having some timing characteristics not entirely scalable with scaling of the system clock frequency. In response to an indication of a change in a frequency of the system clock, the memory controller adapts the part autonomously to enable it to output new digital memory control signals synchronized to the changed system clock and which also have the non scalable timing characteristics. This avoids the need for the processor to adapt the memory controller. Hence the adaptation can be carried out more quickly, leading to less disruption to other parts of the system and means the frequency scaling can be carried out more often.