Nonvolatile Memory Controller Background Reference Positioning
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Solution Overview
Problem
Solid State Drives (SSDs) face increased Bit Error Rates (BER) due to technology shrinkage, leading to decode failures and increased read latency, as conventional flash management techniques extend SSD life but at the cost of higher read latency when retrying failed read operations.
Innovation Solution
A nonvolatile memory system that includes a status circuit and a background reference positioning circuit to identify updated threshold voltage offset values for each page group, allowing for subsequent host-requested reads to use these values, thereby reducing latency and meeting stringent Uncorrectable Bit Error Rate (UBER) requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If read retry operation is performed after decode failure, then SSD lifetime is extended, but read latency increases
Solution Approach 1:
The patent performs preliminary reference positioning operations during background tasks to pre-calculate and store threshold voltage offset values before they are needed during host-requested read operations. This preliminary action prepares the system in advance, so when a read operation is needed, the pre-computed reference values can be immediately applied, avoiding the time-consuming retry process and reducing read latency while maintaining extended SSD lifetime.
2Loss of time
If threshold voltage shift read instruction is used, then read latency is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The system performs self-calibration by automatically determining updated threshold voltage offset values through background reference positioning operations. The flash memory controller itself service-calibrates the threshold voltages by reading representative pages and calculating the necessary offsets, eliminating the need for external precision calibration equipment and reducing manufacturing precision requirements while enabling fast threshold voltage shift read operations.
Data Source
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AI summary
A nonvolatile memory system, a nonvolatile memory controller and a method for reducing latency of a memory controller are disclosed. Upon the occurrence of an endurance event, a retention timer event or a read disturb event at a closed block, background reads of representative pages of each page group of the closed block are performed at offsets to identify a set of updated threshold voltage offset values for each page group of the closed block. When a usage characteristic is determined to meet a usage characteristic threshold, a read circuit performs subsequent host-requested reads using a threshold voltage shift read instruction and reads of pages of the closed block are performed using the set of updated threshold voltage offset values corresponding to the page group of the page being read.