Memory Controller Bank Interleave for CPU Bandwidth
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Solution Overview
Problem
In systems with multiple CPUs sharing a DRAM memory, ensuring sufficient bandwidth for main memory accesses while minimizing latency and overhead is challenging, especially when requests from different CPUs compete for access, leading to increased latency and reduced throughput.
Innovation Solution
A memory access device with a CPU interface circuit and memory controller that arbitrates access requests, allowing multiple CPU access requests to be queued and executed in a single bus cycle using bank interleave, and issuing Precharge commands efficiently to manage concurrent access requests.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple CPUs share a DRAM memory with data buffer, then the number of DRAM memories is reduced, but the bandwidth for CPU access is insufficient
Solution Approach 1:
The patent segments the DRAM memory into multiple banks, allowing simultaneous access to different banks by different CPUs. This enables parallel memory operations, effectively increasing the available bandwidth for CPU accesses without requiring additional DRAM memory chips.
Solution Approach 2:
The patent introduces bank interleaving to add a new dimension to memory access organization. By distributing data across multiple banks and enabling simultaneous access to different banks, the system effectively increases bandwidth without increasing the physical memory capacity.
2Productivity
If the bus width is widened to increase bandwidth, then the bandwidth is improved, but the number of chips used increases
Solution Approach 1:
Instead of widening the bus, the patent segments memory access into parallel operations across multiple banks. Multiple CPUs can simultaneously access different banks, achieving increased bandwidth through parallelism rather than bus width expansion, thus avoiding additional chips.
3Productivity
If the operating frequency is raised to increase bandwidth, then the bandwidth is improved, but the power consumption increases
Solution Approach 1:
The patent achieves increased bandwidth through spatial segmentation into multiple banks that can operate in parallel, rather than increasing the operating frequency. This approach increases throughput without the quadratic power consumption increase associated with higher frequencies.
4Ease of operation
If a main memory request is issued during data flow transfer, then the request is processed, but the latency time increases
Solution Approach 1:
By segmenting the memory into multiple banks, the patent allows main memory requests to be directed to different banks simultaneously with data flow transfers. This parallel access capability eliminates the waiting time that would occur in a single-bank system, significantly reducing latency.
Solution Approach 2:
The patent implements a queue mechanism that holds and prioritizes memory access requests. When bank resources become available, queued requests are processed immediately, reducing the effective latency by preparing requests in advance and rapidly responding when resources are free.
5Loss of energy
If the burst transfer length is increased to reduce overhead, then the overhead is reduced, but the turn around time for main memory requests increases
Solution Approach 1:
The patent segments memory access into bank-level operations, allowing multiple shorter transfers to occur in parallel across different banks. This maintains low overhead by efficiently utilizing the memory interface while avoiding long sequential transfers that would increase turn-around time.
Data Source
AI summary
The present invention includes a plurality of CPUs using memory as main memory, another function block using memory as a buffer, a CPU interface which controls access transfer from the plurality of CPUs to memory, and a DRAM controller for performing arbitration of the access transfer to the memory. Therein, the CPU interface causes access requests from the plurality of CPUs to wait, and receives and stores the address, data transfer mode and data size of each access, notifies the DRAM controller of the access requests, and then, upon receiving grant signals for the access requests, sends information to the DRAM controller according to the grant signals, whereupon the DRAM controller receives the grant signals, and on the basis of the access arbitration, specifies CPUs for which transfers have been granted so as to send the grant signals to the CPU interface.